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楼主 |
发表于 2017-7-27 11:53:22
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- module counter_test;
- reg clk1k;
- reg rst_n;
- reg pinlvkin;
-
- wire feedclko;
- wire[18:0] count1kout;
-
- parameter CYCLE = 1000;
- parameter RST_TIME=3;
-
-
- initial begin
- clk1k = 0;
- forever
- #(CYCLE/2)
- clk1k=~clk1k;
- end
- initial begin
- rst_n = 1;
- #2;
- rst_n = 0;
- #(CYCLE* RST_TIME)
- rst_n = 1;
- end
-
- initial begin
- pinlvkin = 0;
- forever
- #20
- pinlvkin = ~pinlvkin;
- end
- counter uut(
- .clk1k(clk1k),
- .rst_n(rst_n),
- .pinlvkin(pinlvkin),
- .feedclko(feedclko),
- .count1kout(count1kout)
- );
- endmodule
复制代码 回复 12# renfz
这是我修改后代码,还是一样结果
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