Verification Engineer Location: Chengdu;
- Write verification plans according to architecture document
- Writing behavioral models, monitors, and self-checking test benches
- Verify the design at block level and chip level, debug & report bugs
- Develop directed, random, and pseudo-random test cases to fully verify the design.
- Work with other engineering to meet the project goal and resolve issues during verification, FPGA test and validation.
- 3+ years’ experience on Verification
- Experience of Verilog, SystemVerilog, UVM
- Strong DSP and Matlab background is a plus
- Hands on experience of SOC architecture, micro-processor verification, and silicon debug environment