VLSI2006-2016会议ADC论文集合

安东特

VLSI2006-2008论文具体篇名为：
A 500MS/s 5b ADC in 65nm CMOS
A 1.35 GS/s, lOb, 175 mW Time-Interleaved AD Converter in 0.13 μm CMOs
A 1.35 GS/s, 10 b, 175 mW Time-Interleaved AD Converter in 0.13 μm CMOS

VLSI2009论文具体篇名为：
23-1 A 0.92mW 10-bit 50-MS/s SAR ADC in 0.13μm CMOS Process
23-2 A 6-bit 50-MS/s Threshold Configuring SAR ADC in 90-nm Digital CMOS
23-3 A 12b 11MS/s Successive Approximation ADC with two comparators in 0.13μm CMOS
23-4 A 1.3μW 0.6V 8.7-ENOB Successive Approximation ADC in a 0.18?m CMOS


VLSI2010论文具体篇名为：
1.A Zero-Crossing Based 12b 100MS/s Pipelined ADC with Decision Boundary Gap Estimation Calibration
2.A 12b 50MS/s 3.5mW SAR Assisted 2-Stage Pipeline ADC
3.A 9-bit 150-MS/s 1.53-mW Subranged SAR ADC in 90-nm CMOS
4.A 1V 11fJ/Conversion-Step 10bit 10MS/s Asynchronous SAR ADC in 0.18μm CMOS



VLSI2011论文具体篇名为：
14-2 A 96-Channel Full Data Rate Direct Neural Interface in 0.13μm CMOS
14-3 BioBolt: A Minimally-Invasive Neural Interface for Wireless Epidural Recording by Intra-Skin Communication
25-1 A 0.5V 1.1MS/sec 6.3fJ/conversion-step SAR-ADC with Tri-Level Comparator in 40nm CMOS
25-2 A 1-V, 8b, 40MS/s, 113μW Charge-Recycling SAR ADC with a 14μW Asynchronous Controller


VLSI2012论文具体篇名为：
1.A 3.8mW 8b 1GS/s 2b/cycle Interleaving SAR ADC with Compact DAC Structure
2.A 4.5-mW 8-b 750-MS/s 2-b/Step Asynchronous Subranged SAR ADC in 28-nm CMOS Technology
3.A 2.8GS/s 44.6mW Time-Interleaved ADC Achieving 50.9dB SNDR and 3dB Effective Resolution Bandwidth of 1.5GHz in 65nm CMOS
4.A 3.2fJ/c.-s. 0.35V 10b 100KS/s SAR ADC in 90nm CMOS
5.A 34fJ 10b 500 MS/s Partial-Interleaving Pipelined SAR ADC


VLSI2013论文具体篇名为：
SESSION 25 Emerging ADCs
21-1 A 35 mW 8 b 8.8 GS/s SAR ADC with Low-Power Capacitive Reference Buffers in 32 nm Digital SOI CMOS
22-2 A 6b 10GS/s TI-SAR ADC with Embedded 2-Tap FFE/1-Tap DFE in 65nm CMOS
21-3 An 8.5mW 5GS/s 6b Flash ADC with Dynamic Offset Calibration in 32nm CMOS SOI
21-4 A 0.0058mm2 7.0 ENOB 24MS/s 17fJ/conv. Threshold Configuring SAR ADC with Source Voltage Shifting and Interpolation Technique
21-5 A 2.1 mW 11b 410 MS/s Dynamic Pipelined SAR ADC with Background Calibration in 28nm Digital CMOS
22-1 A 10 Gb/s 2-IIR-Tap DFE Receiver with 35 dB Loss Compensation in 65-nm CMOS


VLSI2014论文具体篇名为：
1.A 12-bit 210-MS/s 5.3-mW Pipelined-SAR ADC with a Passive Residue Transfer Technique
2.An 11.5-ENOB 100-MS/s 8mW Dual-Reference SAR ADC in 28nm CMOS
3.A 70 dB SNDR 200 MS/s 2.3 mW dynamic pipelined SAR ADC in 28nm digital CMOS
4.A 12b 160MS/s Synchronous Two-Step SAR ADC Achieving 20.7fJ/step FoM with Opportunistic Digital Background Calibration


VLSI2015论文具体篇名为：
3-2 A 120nW 8b Sub-ranging SAR ADC with Signal-Dependent Charge Recycling for Biomedical Applications
3-3 A 12b 11MS/s successive approximation ADC with two comparators in 0.13μm CMOS
3-4 A 9.35-ENOB, 14.8 fJ/conv.-step Fully-Passive Noise-Shaping SAR ADC
3-5 A 12-Bit 200-MS/s 3.4-mW CMOS ADC with 0.85-V Supply
11-1 A 25GS/s 6b TI Binary Search ADC with Soft-Decision Selection in 65nm CMOS
11-2 A 3-10fJ/conv-step 0.0032mm2 Error-Shaping Alias-Free Asynchronous ADC
11-3 A 6b 46GS/s ADC with >23GHz BW and Sparkle-Code Error Correction
TABLE OF CONTENTS


VLSI2016论文具体篇名为：
1.A 23mW 24GS/s 6b Time-Interleaved Hybrid Two-Step ADC in 28nm CMOS
2.A 56Gb/s PAM4 Wireline Transceiver using a 32-way Time-Interleaved SAR ADC in 16nm FinFET
3.A 0.44fJ/conversion-step 11b 600KS/s SAR ADC with Semi-Resting DAC
4.A 12-bit 1.6 GS/s Interleaved SAR ADC with Dual Reference Shifting and Interpolation Achieving 17.8 fJ/conv-step in 65nm CMOS
5.A 97.99 dB SNDR, 2 kHz BW, 37.1 μW Noise-Shaping SAR ADC with Dynamic Element Matching and Modulation Dither Effect
6.A 18.5-fJ/step VCO-Based 0-1 MASH ΔΣ ADC with Digital Background Calibration
7.Multi-modal Smart Bio-sensing SoC Platform with >80dB SNR 35μA PPG RX Chain
8.An Oscillator Collapse-Based Comparator with Application in a 74.1dB SNDR,20KS/s 15b SAR ADC
9.A 8.2-mW 10-b 1.6-GS/s 4× TI SAR ADC with Fast Reference Charge Neutralization and Background Timing-Skew Calibration in 16-nm CMOS
10.A 14.6mW 12b 800MS/s 4×Time-Interleaved Pipelined SAR ADC achieving 60.8dB SNDR with Nyquist input and sampling timing skew of 60fsrms without calibration

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yanglin0127

回复 1# 安东特


   感谢分享

kiteinsky

大赞，好东西，感谢分享。

sxl0624

非常好的东西

phononwang

thanks

phononwang

thanks

tingyc

thanks

liuhan158

thanks

寒枫

多谢分享

woodhorse

非常好的资料