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[资料] 2010-2013ISSCC会议ADC论文集合

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发表于 2017-4-5 19:17:35 | 显示全部楼层 |阅读模式

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具体文献如下
ISSCC2010年ADC具体文献篇名
Session 21 Overview:Successive-Approximation ADCs
21.1 An 18b 12.5MHz ADC with 93dB SNR
21.2 A 12b 22.5/45MS/s 3.0mW 0.059mm2 CMOS SAR ADC Achieving Over 90dB SFDR                  
21.3 A 0.06mm2 8.9b ENOB 40MS/s Pipelined SAR ADC in 65nm CMOS
21.4 A 10b 50MS/s 820μW SAR ADC with On-Chip Digital Calibration
21.5 A 10b 100MS/s 1.13mW SAR ADC with Binary-Scaled Error Compensation
21.6 A 30fJ/Conversion-Step 8b 0-to-10MS/s Asynchronous SAR ADC in 90nm CMOS
21.7 A 40GS/s 6b ADC in 65nm CMOS
ISSCC_2010_ADC_Spec_and_Testing                                                                    

2010.part1.rar (14.31 MB, 下载次数: 162 )       2010.part2.rar (14.31 MB, 下载次数: 166 )     2010.part3.rar (14.31 MB, 下载次数: 159 )

2010.part4.rar (14.31 MB, 下载次数: 163 )       2010.part5.rar (6.65 MB, 下载次数: 301 )


ISSCC2011年ADC具体文献篇名
10.1 A 480mW 2.6GS/s 10b 65nm CMOS Time-Interleaved ADC with 48.5dB SNDR up to Nyquist
10.2 A 12b 1GS/s SiGe BiCMOS Two-Way Time-Interleaved Pipeline ADC
10.3 An 800MS/s Dual-Residue Pipeline ADC in 40nm CMOS
10.4 A 16b 80MS/s 100mW 77.6dB SNR CMOS Pipeline ADC
10.5 A 0.024mm2 8b 400MS/s SAR ADC with 2b/Cycle and Resistive DAC in 65nm CMOS
10.6 A Resolution-Reconfigurable 5-to-10b 0.4-to-1V Power Scalable SAR ADC
10.7 A 12b 1.25GS/s DAC in 90nm CMOS with >70dB SFDR up to 500MHz
10.8 A 56GS/s 6b DAC in 65nm CMOS with 256×6b Memory

2011.rar (10.97 MB, 下载次数: 158 )


ISSCC2012年ADC具体文献篇名
27.1 A 14b 3/6GHz Current-Steering RF DAC in 0.18μm CMOS with 66dB ACLR at 2.9GHz
27.2 Ring Amplifiers for Switched-Capacitor Circuits
27.3 A 5.37mW 10b 200MS/s Dual-Path Pipelined ADC
27.4 A 13b 315fsrms 2mW 500MS/s 1MHz Bandwidth Highly Digital Time-to-Digital Converter Using Switched Ring Oscillators
27.5 A 1.7mW 11b 250MS/s 2× Interleaved Fully Dynamic Pipelined SAR ADC in 40nm Digital CMOS
27.6 A 90MS/s 11MHz Bandwidth 62dB SNDR Noise-Shaping SAR ADC
27.7 A 70dB DR 10b 0-to-80MS/s Current-Integrating SAR ADC with Adaptive Dynamic Range
27.8 A 7-to-10b 0-to-4MS/s Flexible SAR ADC with 6.5-to-16fJ/conversion-step
27.9 A 31.3fJ/conversion-step 70.4dB SNDR 30MS/s 1.2V Two-Step Pipelined ADC in 0.13μm CMOS

2012.rar (5.66 MB, 下载次数: 131 )


ISSCC2013年ADC具体文献篇名
15.1 A 28fJ/conv-step CT ΔΣ Modulator with 78dB DR and 18MHz BW in 28nm CMOS Using a Highly Digital Multibit Quantizer
15.2 A 2.2/2.7fJ/conversion-step 10/12b 40kS/s SAR ADC with Data-Driven Noise Reduction
15.3 A 71dB-SNDR 50MS/s 4.2mW CMOS SAR ADC by SNR Enhancement Techniques Utilizing Noise
15.4 A 1V 14b Self-Timed Zero-Crossing-Based Incremental ΔΣ ADC
15.5 A 6.3μW 20b Incremental Zoom-ADC with 6ppm INL and 1μV Offset
15.6 A 20b Clockless DAC with Sub-ppm-Linearity 7.5nV/√Hz-Noise and 0.05ppm/°C-Stability
15.7 A 2.4-to-5.2fJ/conversion-step 10b 0.5-to-4MS/s SAR ADC with Charge-Average Switching DAC in 90nm CMOS
15.8 Adaptive Cancellation of Gain and Nonlinearity Errors in Pipelined ADCs
26.1 A 10.3GS/s 6b Flash ADC for 10G Ethernet Applications
26.2 An 11b 3.6GS/s Time-Interleaved SAR ADC in 65nm CMOS
26.3 A 14b 2.5GS/s 8-Way-Interleaved Pipelined ADC with Background Calibration and Digital Dynamic Linearity Correction
26.4 A 3.1mW 8b 1.2GS/s Single-Channel Asynchronous SAR ADC with Alternate Comparators for Enhanced Speed in 32nm Digital SOI CMOS
26.5 An 8.6 ENOB 900MS/s Time-Interleaved 2b/cycle SAR ADC with a 1b/cycle Reconfiguration for Resolution Enhancement
26.6 A 14b 80MS/s SAR ADC with 73.6dB SNDR in 65nm CMOS
26.7 A 12b 1.6GS/s 40mW DAC in 40nm CMOS with >70dB SFDR over Entire Nyquist Bandwidth

2013.rar (9.74 MB, 下载次数: 156 )
发表于 2017-7-9 15:08:00 | 显示全部楼层
不错,多谢
发表于 2017-7-9 18:43:55 | 显示全部楼层
谢谢分享
发表于 2017-7-9 18:46:26 | 显示全部楼层
小飞侠
发表于 2017-7-9 18:58:07 | 显示全部楼层
谢谢分享
发表于 2017-7-9 18:58:56 | 显示全部楼层
谢谢分享
发表于 2018-11-13 13:11:35 | 显示全部楼层
SADFDSHGFKHJLKJ;LK
发表于 2018-11-13 13:14:45 | 显示全部楼层
ZXCCZXVRDFGHJGMCNBV
发表于 2018-11-14 03:18:45 | 显示全部楼层
非常感謝~~~
发表于 2018-11-14 08:42:05 | 显示全部楼层
不错!!!
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