Cadence 上海招聘 FPGA&Memory IP Design Engineer

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Cadence 上海招聘 FPGA&Memory IP Design Engineer, 具体职位描述及职位需求如下，有意者请将简历发至541515639@qq.com：
1.Lead Design Engineer-FPGA

Position Description:   

1. Responsible fordesigning, developing, modifying and productizing hardware based verificationproducts.

2. Perform as individual contributor on FPGA based designprojects involving board design, RTL design, verification and documentation.

3. Work on complex problems related to FPGA design, protocolor system integration level issues, electrical or timing closure issues, RTLdesign or verification methodologies.

4. Create, maintain and track project schedules.

Position Requirements:   

1.The positionrequires BSEE, or equivalent, with a minimum of 5 yrs of industry experience indesigning hardware systems.

2. Must haveexcellent communication skills, both written and verbal.

3. Technicalexpertise in FPGA design for either Altera or Xilinx products is required.

4. Experience in FPGAdesign methodologies including high speed design, serial protocols and FPGAtiming closure is desired.

5. In addition RTLdesign knowledge using verilog is required along with experience in using RTLverification tools and flows.

6. Verification usingCadence simulation products is desired.

7. Experience withscripting languages like Perl, TCL C-shell is strongly recommended.

8. Experience withPCB tools is also desired. Experience with high speed memory interface designis also desired.

9. Candidates with either SAS or arm experience is a plus

2. Lead Design Engineer – Memory Modeling Portfolio

Position Description:

1. Responsible for scheduling, designing, developing, andsupporting IP models of system level memory such as SDRAM (LPDDR, HBM), NANDFlash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS models for use on hardwarebased verification products.

2. Also responsible for updating, maintaining, documenting,and supporting existing system level memory model products.

3. Perform as individual contributor for RTL design,verification, productizing, and documentation of memory IP.

4. Interface with internal and external customers to work ondiverse problems and solutions related to emulation, simulation, orverification.

5. Perform as team member toward cross verification of andcross training in memory IP as well as in developing and using lifecycleprocesses to ensure product quality.

Position Requirements:

Essential:

1. The position requires BSEE, or equivalent, with a minimumof 4 yrs of industry experience in designing hardware systems.

2. RTL design knowledge using Verilog/SystemVerilog isrequired along with experience using RTL verification tools and flows.

3. Experience with team-wide collaboration tools andprocess. Drive and ability to schedule workload and plan own tasks effectively.

4. Must have excellent communication skills with bothwritten and spoken English.

Strongly Recommended:

1. Verification experience using Cadence simulation and/oremulation products is highly desired. 2. Programming experience with scriptinglanguages like Perl, TCL, C-shell is strongly recommended. 3. Experience inmemory sub-system design and operation is strongly recommended.

3. Principal Design Engineer- FPGA Hardware

Position Description:

This is a position in the Vertical Solutions Engineeringteam (VSE) in the Hardware System Verification business unit. The VSE teamdevelops FPGA based boards, known as SpeedBridges that connect the Palladiumsystem to real world external systems. This position is for a Principal DesignEngineer with responsibilities related to developing FPGA based SpeedBridgeboards. The role is based in Shanghai and will add to our expanding team of VSEengineers in our main R&D headquarters within China. The position issupported by local team managers and will work very closely with our productarea team architects based in San Jose, California in the USA.

Key responsibilities

1. To develop protocol expertise and knowledge in a numberof standard protocols such as USB, PCIe, Networking and MIPI.

2. To specialize in a few of these protocols to become anexpert capable of designing complex FPGA based systems to connect ourhigh-performance computing platform (Palladium) to external systems over thestandard protocols being addressed.

3. Develop and lead development of entire FPGA designs andsubsystems, from initial concept to productization and customer deployment.

4. Developing techniques to connect systems using protocolbased methods to overcome speed differences in the systems being connected

5. The ability to write clear concise technicalspecifications in English for the FPGA system being developed. Ranginginitially from smaller sub-systems to entire SpeedBridge designs

6.Be able to propose innovative solutions to system levelissues relating to customer verification of asics in complex system levelhardware and software environments

7. The ability to communicate and work co-cooperatively withother leading experts in the local Shanghai team and with globally remotemanagers and other team members in San Jose in the US

8. Possess excellent Verilog or System Verilog RTL designskills

9. Possess excellent FPGA design skills that includebalancing performance, area, power, complexity and timing in Xilinx and/orAltera FPGA's and their associated design tools

Position Requirements:

1. Bachelors in Electrical Engineering (or equivalentcomputer systems) + 10 years of related experience; Masters + 7 years ofrelated experience; PhD + 5 years of related experience

2. Must have excellent English communication skills, bothwritten and verbal as reports and specifications will be in English and therewill be extensive international video conference collaboration with the US SanJose team

3. Technical expertise in FPGA design for either Altera orXilinx products is required.

4. Experience in FPGA design methodologies including highspeed design, serial protocols and FPGA timing closure is required.

5. Excellent RTL design knowledge using Verilog is required

6. Extensive experience in using RTL simulation verificationtools and flows is required

7. Knowledge of USB3.x and or USB2.0 protocols and overallsystem level experience is desired.

8. Verification using Cadence simulation products isdesired.

9. Experience with scripting languages like Python, Perl,TCL, Unix-shell is strongly recommended.

10. Experience with version control systems such asSubversion (SVN) is also desired.

11. Familiarity with PCB schematics and related board designwould be useful but not required

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