Cadence上海招MMP Design Engineer& FPGA Design Engineer

kengteng

工作地点：浦东芳甸路1155号

简历请投递HR邮箱：cecilyl@cadence.com

1. LeadDesign Engineer – Memory Modeling Portfolio

  

PositionDescription:

1. Responsible for scheduling, designing,developing, and supporting IP models of system level memory such as SDRAM(LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFS modelsfor use on hardware based verification products.

2. Also responsible for updating,maintaining, documenting, and supporting existing system level memory modelproducts.

3. Perform as individual contributor forRTL design, verification, productizing, and documentation of memory IP.

4. Interface with internal and externalcustomers to work on diverse problems and solutions related to emulation,simulation, or verification.

5. Perform as team member toward crossverification of and cross training in memory IP as well as in developing andusing lifecycle processes to ensure product quality.

  

PositionRequirements:

Essential:

1. The position requires BSEE, orequivalent, with a minimum of 4 yrs of industry experience in designinghardware systems.

2. RTL design knowledge usingverilog/SystemVerilog is required along with experience using RTL verificationtools and flows.

3. Experience with team-wide collaborationtools and process. Drive and ability to schedule workload and plan own taskseffectively.

4. Must have excellent communication skillswith both written and spoken English.

StronglyRecommended:

1. Verification experience using Cadencesimulation and/or emulation products is highly desired. 2. Programming experiencewith scripting languages like Perl, TCL, C-shell is strongly recommended. 3.Experience in memory sub-system design and operation is strongly recommended.

2. LeadDesign Engineer

Position Description:   
1. Responsible for designing, developing, modifying and productizinghardware based verification products.

2. Perform as individualcontributor on FPGA based design projects involving board design, RTL design,verification and documentation.

3. Work on complex problemsrelated to FPGA design, protocol or system integration level issues, electricalor timing closure issues, RTL design or verification methodologies.

4. Create, maintain andtrack project schedules.

Position Requirements:    
1.The position requires BSEE, or equivalent, with a minimum of 5 yrs ofindustry experience in designing hardware systems.
2. Must have excellent communication skills, both written and verbal.
3. Technical expertise in FPGA design for either Altera or Xilinx productsis required.
4. Experience in FPGA design methodologies including high speed design, serialprotocols and FPGA timing closure is desired.
5. In addition RTL design knowledge using Verilog is required along withexperience in using RTL verification tools and flows.
6. Verification using Cadence simulation products is desired.
7. Experience with scripting languages like Perl, TCL C-shell is stronglyrecommended.
8. Experience with PCB tools is also desired. Experience with high speed memoryinterface design is also desired.

9. Candidates with eitherUSB or MIPI experience is a plus