B、选择拓扑结构
无源结构：噪声小、功耗低
有源结构：电荷泵不需要宽电压范围、三阶pll不需要电感
In general, there are two design rules that should be followed when using an active loop filter implementation. First, the output of the charge pump should always feed directly into a high-Q capacitor (i.e. a capacitor with minimal series resistance) in order to attenuate its high frequency content before it feeds into the loop filter opamp. The reason for doing so is that the opamp has limited bandwidth and can exhibit nonlinear behavior if it is directly driven with the high frequencies that are present in the charge pump output. The second rule is that the feedback of the opamp should be configured to achieve unity gain from the opamp terminals to its output. By doing so, the input referred noise of the opamp is not amplified in its influence on the loop filter output. The active topologies shown in Figure 11 achieve both of these desired characteristics.
上周发了这篇帖子， 希望将我学习pll的历程记录在这里，能和大家讨论学习。
今天是第一站。
前段时间根据别人论文的Verilog—A建模的pll代码，我在AMS里仿真了，但是觉得有些抽象。所以参考了论坛的一些前辈的建议，选择先使用cppsim工具进行建模，可能这样对环路函数更有直观的感受，当然有些大神建议MATLAB甚至手算，我抱着好用的态度还是先试试cppsim吧。
这周先通过《cppsim_vppsim_primer5》文档大体了解cppsim这一套软件
其次阅读《PLL Design Using the PLL Design Assistant Program》，介绍了用该软件来设计pll的流程，摘录了笔记发在了前面。
了解了设计流程后，通过《Fractional-N Frequency Synthesizer Design Using The PLL Design Assistant and CppSim Programs》介绍GSM的pll实例来加深并细化前面一篇文档介绍的设计流程，参数的提取与设定。但是还没看完，所以笔记就稍后两天再传吧
/3 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2016-6-29 23:02:45
楼主
