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发表于 2019-10-15 08:16:27
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既然值得参考就来一段 RX engine的code (PCIE2.0 4x)-------------------------------------------------------------------------------
-- Project : Series-7 Integrated Block for PCI Express
-- File : PIO_RX_ENGINE.vhd for GEN2 128 bits
-- Version : 3.3
----
---- Description: Local-Link Receive Unit.
----
----------------------------------------------------------------------------------
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
entity PIO_RX_ENGINE_DMA_128bit is
generic(
C_DATA_WIDTH : integer range 64 to 128 := 64;
TCQ : time := 1 ps
);
port(
i_clk : in std_logic;
i_rst_n : in std_logic;
i_pcie_phy_rdy : in std_logic;
--
-- Receive AXI-S interface from PCIe core
--
o_axis_rx_tready : out std_logic;
i_axis_rx_tdata : in std_logic_vector(127 downto 0);
i_axis_rx_tkeep : in std_logic_vector(15 downto 0); -- not used ???
i_axis_rx_tlast : in std_logic;
i_axis_rx_tvalid : in std_logic;
i_axis_rx_tuser : in std_logic_vector(21 downto 0);
o_cfg_err_cpl_unexpect : out std_logic;
o_cfg_err_posted : out std_logic;
--
-- interface to PCIE_TX_ENGINE
o_req_tc : out std_logic_vector(2 downto 0);
o_req_td : out std_logic;
o_req_ep : out std_logic;
o_req_attr : out std_logic_vector(1 downto 0);
o_req_len : out std_logic_vector(9 downto 0);
o_req_rid : out std_logic_vector(15 downto 0);
o_req_tag : out std_logic_vector(7 downto 0);
o_req_be : out std_logic_vector(7 downto 0);
o_req_addr : out std_logic_vector(25 + 2 downto 0); -- 16Mx4 DWORD address
--
-- Memory interface used to save 1 DW data received
-- on Memory Write 32 TLP. Data extracted from
-- inbound TLP is presented to the Endpoint memory
-- unit. Endpoint memory unit reacts to wr_en
-- assertion and asserts wr_busy when it is
-- processing written information.
--
-- Memory Read data handshake with Completion
-- transmit unit. Transmit unit reponds to
-- o_req_compl assertion and responds with i_compl_done
-- assertion when a Completion w/ data is transmitted.
--
o_BAR_hit : out std_logic_vector(7 downto 0);
o_req_compl : out std_logic;
o_req_compl_with_data : out std_logic;
i_compl_done : in std_logic;
-- for DMA write
o_tx_TAG : out std_logic_vector(4 downto 0);
o_tx_TAG_valid : out std_logic;
i_tx_TAG_ack : in std_logic;
--
i_Tx2Rx_CPLD_para_reset : in std_logic;
i_Tx2Rx_CPLD_para_wren : in std_logic;
i_Tx2Rx_CPLD_para_din : in std_logic_vector(42 downto 0);
o_Tx2Rx_CPLD_para_full : out std_logic;
--
o_DMA_wr_active : out std_logic; -- used by PCIE_DMA_Controller to determine end of DMA
o_DMA_wr_error : out std_logic; -- should trigger i_Tx2Rx_CPLD_para_reset
o_DMA_wr_timeout : out std_logic; -- timeout error is cleared when DMA_wr_active = '0'
-- PCI-E error
o_cfg_err_cpl_timeout_n : out std_logic;
-- interface to local memory
o_wr_select : out std_logic_vector(3 downto 0);
o_wr_en : out std_logic;
o_wr_DW_cnt : out std_logic_vector(9 downto 0);
o_wr_addr : out std_logic_vector(27 downto 0); -- Memory Write Address -- 29 bits for 4g 28:0 DW address 28:2 DW address no need lsb 1 bit
o_wr_be : out std_logic_vector(3 downto 0); -- Memory Write Byte Enable -- local mem be control change to 4 bits 20190206 Ting
o_wr_mask : out std_logic_vector(15 downto 0);
o_wr_data : out std_logic_vector(127 downto 0); -- Memory Write Data why original is 32???
--wr_en : out std_logic; -- Memory Write Enable
i_wr_busy : in std_logic; -- Memory Write Busy
-- test points
o_Header_DW01 : out std_logic_vector(63 downto 0);
o_cpl_ATTR : out std_logic_vector(1 downto 0);
o_Error_hdr_strobe1 : out std_logic;
o_Header_DW2 : out std_logic_vector(31 downto 0);
o_Error_hdr_strobe2 : out std_logic;
o_ERROR_CPL_ATTR : out std_logic;
o_ERROR_CPLD_ATTR : out std_logic;
o_ERROR_CPLD_state : out std_logic_vector(1 downto 0);
o_ERROR_DMA_WR_CNT : out std_logic;
o_ERROR_DMA_TAG : out std_logic;
o_ERROR_DMA_CPLD_tag : out std_logic_vector(4 downto 0);
o_ERROR_UNSUPPORTED_TLP : out std_logic
);
end PIO_RX_ENGINE_DMA_128bit;
architecture rtl of PIO_RX_ENGINE_DMA_128bit is
attribute DowngradeIPIdentifiedWarnings : string;
attribute DowngradeIPIdentifiedWarnings of rtl : architecture is "yes";
constant RX_MEM_RD32_FMT_TYPE : std_logic_vector(6 downto 0) := "0000000"; -- Hex 00
constant RX_MEM_WR32_FMT_TYPE : std_logic_vector(6 downto 0) := "1000000"; -- Hex 40
constant RX_MEM_RD64_FMT_TYPE : std_logic_vector(6 downto 0) := "0100000"; -- Hex 20
constant RX_MEM_WR64_FMT_TYPE : std_logic_vector(6 downto 0) := "1100000"; -- Hex 60
constant RX_CPL_FMT_TYPE : std_logic_vector(6 downto 0) := "0001010"; -- Hex 0A completion with no data (DMA read error?)
constant RX_CPLD_FMT_TYPE : std_logic_vector(6 downto 0) := "1001010"; -- Hex 4A completion with data (DMA read)
signal tlp_type : std_logic_vector(7 downto 0);
signal axis_rx_tready : std_logic;
signal BAR_hit : std_logic_vector(7 downto 0);
signal BAR_hit_hold : std_logic_vector(7 downto 0);
signal in_packet_reg : std_logic;
signal RX_FMT_TYPE : std_logic_vector(6 downto 0);
-- write control
signal use_1stBE : std_logic;
signal single_DW_end : std_logic;
signal two_DW_end : std_logic;
signal three_DW_end : std_logic;
signal wr_be : std_logic_vector(3 downto 0);
signal wr_mask : std_logic_vector(3 downto 0);
signal write_1STBE : std_logic_vector(3 downto 0);
signal write_LASTBE : std_logic_vector(3 downto 0);
--signal write_DW_address : std_logic_vector(23+2 downto 0); -- 16Mx4 DW
signal wr_addr : std_logic_vector(27 downto 0);
signal wr_addr_temp : std_logic_vector(27 downto 0); --- word addr
signal req_len : std_logic_vector(9 downto 0);
signal wr_DW_cnt : std_logic_vector(9 downto 0);
signal wr_DW_cnt_temp : std_logic_vector(9 downto 0);
signal bar2_data_2dw : std_logic_vector(31 downto 0);
alias wr_DW_cnt_alias : std_logic_vector(9 downto 0) is i_axis_rx_tdata(9 downto 0);
alias wr_DW_cnt_alias_M : std_logic_vector(9 downto 0) is i_axis_rx_tdata(73 downto 64);
-- little-endian to big-endian
signal wr_data_swap : std_logic_vector(127 downto 0);
signal wr_data : std_logic_vector(127 downto 0);
signal wr_data_temp : std_logic_vector(127 downto 0);
-- DMA
signal DMA_wr_addr : std_logic_vector(27 downto 0); -- 16Mx4 DW
signal DMA_wr_DW_cnt : std_logic_vector(9 downto 0);
-- timeout in 10 ms to 50 ms
signal DMA_timeout_cnt : std_logic_vector(27 downto 0);
signal DMA_timeout_cnt_en : std_logic;
signal DMA_wr_timeout : std_logic;
signal DMA_timeout_d1 : std_logic;
-- 20 ms = 20000 us
-- 20000 x 250 = 1250000 = 4C4B40
constant c_TIME_OUT : std_logic_vector(27 downto 0) := X"04C4B40";
--
signal pcie_phy_rdy_d1 : std_logic;
---------------------------------------------------------------------
component DMA_CPLD_service_r1
generic(
g_concurrent_CPLDs : integer := 4;
g_total_tags : integer := 16
);
port(
i_clk : in std_logic;
i_rst_n : in std_logic;
--
i_Tx2Rx_CPLD_para_reset : in std_logic;
i_Tx2Rx_CPLD_para_wren : in std_logic;
i_Tx2Rx_CPLD_para_din : in std_logic_vector(42 downto 0);
o_Tx2Rx_CPLD_para_full : out std_logic;
-- from current CPLD in
i_cpld_tag_valid : in std_logic;
i_cpld_tag : in std_logic_vector(4 downto 0);
i_cpld_REQ_LENGTH : in std_logic_vector(9 downto 0);
o_DMA_wr_addr : out std_logic_vector(27 downto 0);
o_DMA_wr_DW_cnt : out std_logic_vector(9 downto 0);
o_tag_match : out std_logic; -- 2 clocks delay from i_cpld_tag_valid
o_error_DW_cnt : out std_logic; -- error if i_cpld_REQ_LENGTH > o_DMA_wr_DW_cnt
o_error_TAG_No_Match : out std_logic; -- error if no TAG match
--
o_DMA_wr_active : out std_logic;
-- from TX engine
i_tx_TAG_ack : in std_logic;
o_tx_TAG : out std_logic_vector(4 downto 0);
o_tx_TAG_valid : out std_logic
);
end component;
signal cpld_tag_valid : std_logic := '0';
signal srv_DMA_wr_addr : std_logic_vector(27 downto 0) := (others => '0');
signal srv_DMA_wr_DW_cnt : std_logic_vector(9 downto 0) := (others => '0');
signal srv_tag_match : std_logic;
signal srv_error_DW_cnt : std_logic;
signal srv_error_TAG_No_Match : std_logic;
signal DMA_wr_active : std_logic;
signal cpl_TAG : std_logic_vector(7 downto 0) := (others => '0');
signal o_axis_rx_tready_v6pcie0 : std_logic;
signal axis_rx_tdata_d : std_logic_vector(127 downto 0);
type state_type is (
PIO_128_RX_RST_STATE,
PIO_128_RX_MEM_RD32_DW1DW2,
PIO_128_RX_MEM_WR32_BAR0,
PIO_128_RX_MEM_WR32_BAR0_MID,
--PIO_128_RX_MEM_WR32_BAR0_DW,
PIO_128_RX_MEM_WR32_BAR2,
PIO_128_RX_MEM_WR32_BAR2_MID,
PIO_128_RX_MEM_WR32_M_SOF,
PIO_128_RX_MEM_WR32_M_SOF_2, -- need BAR0 more than 1DW wr
PIO_128_RX_WAIT_STATE,
--DELAY_ONE_CYCLE,
-- DMA operation
PIO_DMA_RX_CPLD_CHK_DMA,
PIO_DMA_RX_CPLD_CHK_DMA_R_SOF,
PIO_DMA_RX_CPLD_WR_R_SOF, -- continue to write to BAR0
PIO_DMA_RX_CPLD_RSOF,
PIO_DMA_RX_CPLD,
PIO_DMA_RX_CPL_ERROR,
PIO_DMA_RX_CPL_ERROR_2,
PIO_DMA_RX_CPLD_ERROR,
PIO_DMA_RX_CPLD_ERROR_2
);
signal state : state_type;
signal wr_en : std_logic;
signal wr_busy : std_logic;
signal mem32_o_BAR_hit_n : std_logic;
signal mem64_o_BAR_hit_n : std_logic;
signal erom_o_BAR_hit_n : std_logic;
--signal o_BAR_hit_select : std_logic_vector(3 downto 0);
signal region_select : std_logic_vector(1 downto 0);
signal state_ascii : String(1 to 20) := " ";
signal sof_present : std_logic;
signal sof_right : std_logic;
signal sof_mid : std_logic;
signal axis_rx_tvalid : std_logic;
signal wr_en_mid_d : std_logic;
signal debug_rx_state : std_logic_vector(3 downto 0);
signal wait_state_time_out_cnt : std_logic_vector(7 downto 0);
attribute mark_debug : string;
attribute keep : string;
-- attribute mark_debug of debug_rx_state : signal is "true";
-- attribute mark_debug of srv_error_DW_cnt : signal is "true";
-- attribute mark_debug of srv_error_TAG_No_Match : signal is "true";
--attribute mark_debug of i_compl_done : signal is "true";
--attribute mark_debug of wr_busy : signal is "true";
--attribute mark_debug of wait_state_time_out_cnt : signal is "true";
--attribute mark_debug of tlp_type : signal is "true";
begin
o_axis_rx_tready <= o_axis_rx_tready_v6pcie0;
o_BAR_hit <= "0000" & BAR_hit(3 downto 0);
o_wr_addr <= wr_addr;
o_req_len <= req_len;
o_wr_en <= wr_en;
-- change from little-endian to big-endian
-- BAR 0 MEM 32 WR 32 RD 1DW 2DW 3DW ......
-- BAR 1 2 3 MEM 32 WR 32 RD only support 1 DW 32 bits write data
-- BAR 0 DMA operation
-- (rx_bar_hit[0])m_axis_rx_tuser[2]: BAR0
-- (rx_bar_hit[1])m_axis_rx_tuser[3]: BAR1
-- (rx_bar_hit[2])m_axis_rx_tuser[4]: BAR2
-- (rx_bar_hit[3])m_axis_rx_tuser[5]: BAR3
-- (rx_bar_hit[4])m_axis_rx_tuser[6]: BAR4
-- (rx_bar_hit[5])m_axis_rx_tuser[7]: BAR5
--o_wr_data <= wr_data(103 downto 96) & wr_data(111 downto 104) & -- Only in 128 bits write bar0 need reordering
--wr_data(119 downto 112) & wr_data(127 downto 120) & wr_data(71 downto 64) & wr_data(79 downto 72) & wr_data(87 downto 80) & wr_data(95 downto 88) & wr_data(39 downto 32) & wr_data(47 downto 40) & wr_data(55 downto 48) & wr_data(63 downto 56) & wr_data(7 downto 0) & wr_data(15 downto 8) & wr_data(23 downto 16) & wr_data(31 downto 24) when (state = PIO_128_RX_MEM_WR32_BAR0) or (state = PIO_128_RX_MEM_WR32_BAR0_MID) else wr_data; -- to BAR_0
o_wr_data <= wr_data;
RX_FMT_TYPE <= i_axis_rx_tdata(94 downto 88) when (sof_mid = '1' and state = PIO_128_RX_RST_STATE)
else i_axis_rx_tdata(30 downto 24) when (sof_mid = '0' and state = PIO_128_RX_RST_STATE)
--else i_axis_rx_tdata(30 downto 24) when (sof_mid = '0' and state = PIO_128_RX_RST_STATE)
--else i_axis_rx_tdata(30 downto 24) when (sof_mid = '0' and state = PIO_128_RX_RST_STATE)
;
--cpld_tag_valid <= '1' when (RX_FMT_TYPE = RX_CPLD_FMT_TYPE and state = PIO_128_RX_RST_STATE and srv_tag_match /= '1' and sof_mid = '1' ) else
-- '1' when (tlp_type = RX_CPLD_FMT_TYPE and state = PIO_DMA_RX_CPLD_CHK_DMA and srv_tag_match /= '1' and sof_mid = '0' and i_axis_rx_tvalid = '1' ) else
-- '0';
o_DMA_wr_active <= DMA_wr_active;
-- Drive referenced outputs
o_wr_DW_cnt <= wr_DW_cnt;
o_wr_be <= "1111";
sof_present <= i_axis_rx_tuser(14);
sof_right <= not (i_axis_rx_tuser(13)) and sof_present;
sof_mid <= i_axis_rx_tuser(13) and sof_present;
wr_busy <= i_wr_busy;
DMA_CPLD_service_1 : DMA_CPLD_service_r1
generic map(
g_concurrent_CPLDs => 4,
g_total_tags => 16
)
port map(
i_clk => i_clk,
i_rst_n => i_rst_n,
--
i_Tx2Rx_CPLD_para_reset => i_Tx2Rx_CPLD_para_reset,
i_Tx2Rx_CPLD_para_wren => i_Tx2Rx_CPLD_para_wren,
i_Tx2Rx_CPLD_para_din => i_Tx2Rx_CPLD_para_din,
o_Tx2Rx_CPLD_para_full => o_Tx2Rx_CPLD_para_full,
-- from current CPLD in
i_cpld_tag_valid => cpld_tag_valid,
i_cpld_tag => cpl_TAG(4 downto 0),
i_cpld_REQ_LENGTH => wr_DW_cnt,
o_DMA_wr_addr => srv_DMA_wr_addr,
o_DMA_wr_DW_cnt => srv_DMA_wr_DW_cnt,
o_tag_match => srv_tag_match, -- 2 clocks delay from i_cpld_tag_valid
o_error_DW_cnt => srv_error_DW_cnt, -- error if i_cpld_REQ_LENGTH > o_DMA_wr_DW_cnt
o_error_TAG_No_Match => srv_error_TAG_No_Match, -- error if no TAG match
--
o_DMA_wr_active => DMA_wr_active,
-- from TX engine
i_tx_TAG_ack => i_tx_TAG_ack,
o_tx_TAG => o_tx_TAG,
o_tx_TAG_valid => o_tx_TAG_valid
);
process(i_clk, i_rst_n)
begin
if (i_rst_n = '0') then
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
o_req_compl <= '0' after TCQ;
o_req_compl_with_data <= '0' after TCQ;
o_req_tc <= (others => '0') after TCQ;
o_req_td <= '0' after TCQ;
o_req_ep <= '0' after TCQ;
o_req_attr <= (others => '0') after TCQ;
req_len <= (others => '0') after TCQ;
o_req_rid <= (others => '0') after TCQ;
o_req_tag <= (others => '0') after TCQ;
o_req_be <= (others => '0') after TCQ;
o_req_addr <= (others => '0') after TCQ;
wr_be <= (others => '0') after TCQ;
wr_data <= (others => '0') after TCQ;
wr_data_temp <= (others => '0') after TCQ;
o_wr_mask <= "0000000000000000" after TCQ;
state <= PIO_128_RX_RST_STATE after TCQ;
tlp_type <= (others => '0') after TCQ;
wr_DW_cnt <= (others => '0') after TCQ; -- count Double Words in write operation
wr_DW_cnt_temp <= (others => '0') after TCQ;
use_1stBE <= '1';
single_DW_end <= '1';
wr_mask <= (others => '0');
wr_addr <= (others => '0');
wr_addr_temp <= (others => '0');
o_wr_select <= (others => '0');
o_DMA_wr_error <= '0';
DMA_wr_addr <= (others => '0');
DMA_wr_DW_cnt <= (others => '0');
o_Header_DW01 <= (others => '0');
o_Error_hdr_strobe1 <= '0';
o_Header_DW2 <= (others => '0');
o_Error_hdr_strobe2 <= '0';
o_cpl_ATTR <= (others => '0');
o_ERROR_CPL_ATTR <= '0';
o_ERROR_CPLD_ATTR <= '0';
o_ERROR_DMA_WR_CNT <= '0';
o_ERROR_DMA_TAG <= '0';
o_ERROR_UNSUPPORTED_TLP <= '0';
o_cfg_err_cpl_unexpect <= '0';
o_cfg_err_posted <= '0';
--cpld_tag_valid <= '0';
--
DMA_timeout_cnt <= (others => '0');
DMA_timeout_cnt_en <= '0';
DMA_wr_timeout <= '0';
DMA_timeout_d1 <= '0';
wr_en_mid_d <= '0';
in_packet_reg <= '0';
pcie_phy_rdy_d1 <= '0';
cpld_tag_valid <= '0';
debug_rx_state <= "0000";
wait_state_time_out_cnt <= (others => '0');
--o_wr_be <= (others => '0');
elsif rising_edge(i_clk) then
wr_en <= '0' after TCQ;
--o_req_compl <= '0' after TCQ;
--o_req_compl_with_data <= '0' after TCQ;
o_DMA_wr_error <= '0';
o_Error_hdr_strobe1 <= '0';
o_Error_hdr_strobe2 <= '0';
o_cfg_err_cpl_unexpect <= '0';
o_cfg_err_posted <= '0';
--o_wr_be <= (others => '0');
wait_state_time_out_cnt <= (others => '0');
-- DMA write timeout timer
DMA_wr_timeout <= '0';
DMA_timeout_d1 <= DMA_wr_timeout;
DMA_timeout_cnt <= (others => '0');
DMA_timeout_cnt_en <= DMA_wr_active;
axis_rx_tvalid <= i_axis_rx_tvalid;
if DMA_timeout_cnt_en = '1' then
DMA_timeout_cnt <= DMA_timeout_cnt + 1;
if DMA_timeout_cnt = c_TIME_OUT then
DMA_wr_timeout <= '1';
end if;
end if;
if DMA_wr_timeout = '1' then
o_DMA_wr_timeout <= '1';
end if;
if DMA_timeout_cnt_en = '0' then
o_DMA_wr_timeout <= '0';
end if;
o_cfg_err_cpl_timeout_n <= '1';
if DMA_wr_timeout = '1' and DMA_timeout_d1 = '0' then
o_cfg_err_cpl_timeout_n <= '0';
end if;
case state is
when PIO_128_RX_RST_STATE =>
debug_rx_state <= "0000";
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
wr_mask <= (others => '0');
use_1stBE <= '1';
wr_DW_cnt_temp <= (others => '0') after TCQ;
wr_DW_cnt <= (others => '0') after TCQ;
if (((i_axis_rx_tvalid) and (o_axis_rx_tready_v6pcie0)) = '1') then
if (i_axis_rx_tuser(5 downto 2) /= "0000") then -- Not DMA packet hit Bar0~3
-- tuser[2] BAR0 -- tuser[3] BAR1 -- tuser[4] BAR2 -- tuser[5] BAR3
if ((sof_mid) = '1') then
tlp_type <= i_axis_rx_tdata(95 downto 88) after TCQ;
req_len <= i_axis_rx_tdata(73 downto 64) after TCQ;
BAR_hit <= i_axis_rx_tuser(9 downto 2);
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
--case is
case RX_FMT_TYPE is -- i_axis_rx_tdata(94 downto 88)
when RX_MEM_RD32_FMT_TYPE =>
o_req_tc <= i_axis_rx_tdata(86 downto 84) after TCQ;
o_req_td <= i_axis_rx_tdata(79) after TCQ;
o_req_ep <= i_axis_rx_tdata(78) after TCQ;
o_req_attr <= i_axis_rx_tdata(77 downto 76) after TCQ;
o_req_rid <= i_axis_rx_tdata(127 downto 112) after TCQ;
o_req_tag <= i_axis_rx_tdata(111 downto 104) after TCQ;
o_req_be <= i_axis_rx_tdata(103 downto 96) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_MEM_RD32_DW1DW2 after TCQ;
when RX_MEM_WR32_FMT_TYPE => -- mid header -- 3DW H1H0XX -- XXD0H2
o_req_tc <= i_axis_rx_tdata(86 downto 84) after TCQ;
o_req_td <= i_axis_rx_tdata(79) after TCQ;
o_req_ep <= i_axis_rx_tdata(78) after TCQ;
o_req_attr <= i_axis_rx_tdata(77 downto 76) after TCQ;
o_req_rid <= i_axis_rx_tdata(127 downto 112) after TCQ;
o_req_tag <= i_axis_rx_tdata(111 downto 104) after TCQ;
o_req_be <= i_axis_rx_tdata(103 downto 96) after TCQ;
write_LASTBE <= i_axis_rx_tdata(103 downto 100) after TCQ;
write_1STBE <= i_axis_rx_tdata(99 downto 96) after TCQ;
wr_DW_cnt <= i_axis_rx_tdata(73 downto 64) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
-- BE control
if use_1stBE = '1' then
use_1stBE <= '0';
-- o_wr_be <= i_axis_rx_tdata(99 downto 96); --write_1STBE;
end if;
--if i_axis_rx_tdata(73 downto 64) = 1 then --write_DW_cnt = 1 then
-- if use_1stBE = '0' then
-- o_wr_be <= i_axis_rx_tdata(103 downto 100); --write_LASTBE;
-- end if;
--end if;
state <= PIO_128_RX_MEM_WR32_M_SOF after TCQ; -- DATA IS IN THE NEXT CYCLE
when others => -- other TLPs not supported
state <= PIO_128_RX_RST_STATE;
o_Error_hdr_strobe1 <= '1';
o_ERROR_UNSUPPORTED_TLP <= '1';
end case;
else -- Right side sof_mid = '0'
tlp_type <= i_axis_rx_tdata(31 downto 24) after TCQ;
req_len <= i_axis_rx_tdata(9 downto 0) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
BAR_hit <= i_axis_rx_tuser(9 downto 2);
case RX_FMT_TYPE is --i_axis_rx_tdata(30 downto 24) is -- 7 bits tlp TYPE
when RX_MEM_RD32_FMT_TYPE => -- tell TX engine to send data to pc Hex 00
--if (i_axis_rx_tdata(9 downto 0) = "0000000001") then
o_req_tc <= i_axis_rx_tdata(22 downto 20) after TCQ;
o_req_td <= i_axis_rx_tdata(15) after TCQ;
o_req_ep <= i_axis_rx_tdata(14) after TCQ;
o_req_attr <= i_axis_rx_tdata(13 downto 12) after TCQ;
o_req_rid <= i_axis_rx_tdata(63 downto 48) after TCQ;
o_req_tag <= i_axis_rx_tdata(47 downto 40) after TCQ;
o_req_be <= i_axis_rx_tdata(39 downto 32) after TCQ;
--lower qw
o_req_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ; --DW address
o_req_compl <= '1' after TCQ;
o_req_compl_with_data <= '1' after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ; --ask pc to wait
o_wr_select <= "1000" after TCQ; -- ONLY BAR3?
state <= PIO_128_RX_WAIT_STATE after TCQ;
--else
-- state <= PIO_128_RX_RST_STATE after TCQ;
-- end if;
when RX_MEM_WR32_FMT_TYPE => --3DW Hex 40 eg, D0 H2 H1 H0 one packet 40000001 0000000F 940F7C04 00000000
-- change all addr to DW addr same as mx300e
o_req_tc <= i_axis_rx_tdata(22 downto 20) after TCQ;
o_req_td <= i_axis_rx_tdata(15) after TCQ;
o_req_ep <= i_axis_rx_tdata(14) after TCQ;
o_req_attr <= i_axis_rx_tdata(13 downto 12) after TCQ;
o_req_rid <= i_axis_rx_tdata(63 downto 48) after TCQ;
o_req_tag <= i_axis_rx_tdata(47 downto 40) after TCQ;
o_req_be <= i_axis_rx_tdata(39 downto 32) after TCQ;
write_LASTBE <= i_axis_rx_tdata(39 downto 36) after TCQ;
write_1STBE <= i_axis_rx_tdata(35 downto 32) after TCQ;
wr_DW_cnt <= i_axis_rx_tdata(9 downto 0) - 1 after TCQ;
wr_en <= '0' after TCQ;
o_wr_select <= "0000" after TCQ;
wr_addr <= (others => '0');
-- BE control
if use_1stBE = '1' then
use_1stBE <= '0';
-- o_wr_be <= i_axis_rx_tdata(35 downto 32); --write_1STBE;
end if;
if i_axis_rx_tdata(9 downto 0) = 1 then --write_DW_cnt = 1 then
if use_1stBE = '0' then
-- o_wr_be <= i_axis_rx_tdata(39 downto 36); --write_LASTBE;
end if;
end if;
if (i_axis_rx_tuser(5) = '1') AND (i_axis_rx_tvalid = '1') then -- BAR 3 OR (i_axis_rx_tuser(4) = '1') OR (i_axis_rx_tuser(5) = '1') then
wr_en <= '1' after TCQ;
o_wr_select <= "1000" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ; --change from 93 to 91
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
elsif (i_axis_rx_tuser(4) = '1') AND (i_axis_rx_tvalid = '1') then -- BAR2
if (i_axis_rx_tdata(9 downto 0) = "0000000001") then -- just 1 DW
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ;
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
end if;
if ((i_axis_rx_tdata(9 downto 0) > "000000001")) then -- 2 DW
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ;
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ; -- bug
state <= PIO_128_RX_MEM_WR32_BAR2 after TCQ;
end if;
elsif (i_axis_rx_tuser(3) = '1') AND (i_axis_rx_tvalid = '1') then --BAR1
--if (wr_DW_cnt /= "000000000") then
wr_en <= '1' after TCQ;
o_wr_select <= "0010" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ;
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
--end if;
elsif (i_axis_rx_tuser(2) = '1') AND (i_axis_rx_tvalid = '1') then -- BAR 0 data more than 1DW goto next wr stage
if (wr_DW_cnt_alias <= "0000000001") then
wr_en <= '1' after TCQ;
o_wr_select <= "0001" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ; --
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
elsif (wr_DW_cnt_alias > "0000000001") then
wr_en <= '0' after TCQ;
o_wr_select <= "0001" after TCQ;
wr_DW_cnt <= i_axis_rx_tdata(9 downto 0);
wr_addr_temp <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(91 downto 66) after TCQ;
wr_data_temp <= i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & x"000000000000000000000000" after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_MEM_WR32_BAR0 after TCQ;
end if;
end if;
when others => -- other TLPs not supported
state <= PIO_128_RX_RST_STATE;
o_Error_hdr_strobe1 <= '1';
o_ERROR_UNSUPPORTED_TLP <= '1';
end case;
end if; -- SOF judgment
else -- DMA from here i_axis_rx_tuser(5 downto 2) = "0000" No mem selected
-- ???????The data flow is DMA wr CPLD 1. write select 2. data address from packet 3. data write to BAR0 address from packet
-- FIFO in BAR0 has data and has a req to arbiter
-- Finally data from packet write to address in DDR
-- the response from DMA write
if ((sof_mid) = '1') then -- CPLD in middle
tlp_type <= i_axis_rx_tdata(95 downto 88) after TCQ;
req_len <= i_axis_rx_tdata(73 downto 64) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
--case i_axis_rx_tdata(94 downto 88) is
case RX_FMT_TYPE is
when RX_CPL_FMT_TYPE =>
o_cpl_ATTR <= i_axis_rx_tdata(77 downto 76);
if i_axis_rx_tdata(77 downto 76) /= 0 then -- if attr not 0 error happened
o_ERROR_CPL_ATTR <= '1';
o_Error_hdr_strobe1 <= '1';
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
o_axis_rx_tready_v6pcie0 <= '1';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_DMA_RX_CPL_ERROR;
end if;
-- completion with data, response for DMA write
-- 4A000002 -------- ADDRESS -------- DW1 DW2
-- 00000008_4A000002_00000000_00000000
-- 00000000_2211008_7766554433_01000020
when RX_CPLD_FMT_TYPE =>
o_axis_rx_tready_v6pcie0 <= '0';
tlp_type <= i_axis_rx_tdata(95 downto 88);
wr_DW_cnt <= i_axis_rx_tdata(73 downto 64);
o_cpl_ATTR <= i_axis_rx_tdata(77 downto 76);
--if ((i_axis_rx_tdata(73 downto 65) = "00000000") AND (i_axis_rx_tdata(64) = '1')) then -- just 1 DW response
-- single_DW_end <= '1';
--end if;
--if (i_axis_rx_tdata(73 downto 66) = "00000000") AND (i_axis_rx_tdata(65 downto 64) = "10") then -- 2 DW
-- two_DW_end <= '1';
--end if;
--if (i_axis_rx_tdata(73 downto 66) = "00000000") AND (i_axis_rx_tdata(65 downto 64) = "11") then -- 3 DW
-- three_DW_end <= '1';
--end if;
if use_1stBE = '1' then
use_1stBE <= '0';
end if;
if i_axis_rx_tdata(77 downto 76) /= 0 then
o_ERROR_CPLD_ATTR <= '1';
o_Error_hdr_strobe1 <= '1';
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
axis_rx_tready <= '0';
state <= PIO_DMA_RX_CPLD_ERROR; -- 20110926 lsha, removed cpl_ATTR /= 0 error
end if;
state <= PIO_DMA_RX_CPLD_CHK_DMA; -- remove RX_CPLD_1 128 bits packet
when others => -- other TLPs not supported
state <= PIO_128_RX_RST_STATE;
o_Error_hdr_strobe1 <= '1';
o_ERROR_UNSUPPORTED_TLP <= '1';
end case;
else -- RIGHT SIDE SOF DMA
tlp_type <= i_axis_rx_tdata(31 downto 24) after TCQ;
req_len <= i_axis_rx_tdata(9 downto 0) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
--case i_axis_rx_tdata(30 downto 24) is -- tlp TYPE
case RX_FMT_TYPE is
when RX_CPL_FMT_TYPE => -- Completion without data not supported
o_cpl_ATTR <= i_axis_rx_tdata(13 downto 12);
if i_axis_rx_tdata(13 downto 12) /= 0 then
o_ERROR_CPL_ATTR <= '1';
o_Error_hdr_strobe1 <= '1';
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
o_axis_rx_tready_v6pcie0 <= '1';
state <= PIO_DMA_RX_CPL_ERROR;
end if;
-- completion with data, response from DMA write
when RX_CPLD_FMT_TYPE =>
o_axis_rx_tready_v6pcie0 <= '0';
tlp_type <= i_axis_rx_tdata(31 downto 24);
wr_DW_cnt <= i_axis_rx_tdata(9 downto 0);
o_cpl_ATTR <= i_axis_rx_tdata(13 downto 12);
if use_1stBE = '1' then
use_1stBE <= '0';
end if;
if (i_axis_rx_tvalid = '1') then
cpl_TAG <= i_axis_rx_tdata(79 downto 72); -- H2
cpld_tag_valid <= '1';
--wr_data_temp <= x"000000000000000000000000" & i_axis_rx_tdata(127 downto 96);
wr_data_temp <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120);
state <= PIO_DMA_RX_CPLD_CHK_DMA_R_SOF;
end if;
when others => -- other TLPs not support
state <= PIO_128_RX_RST_STATE;
o_Error_hdr_strobe1 <= '1';
o_ERROR_UNSUPPORTED_TLP <= '1';
end case;
end if; -- end DMA case
end if; -- MEM OR DMA
end if; --valid
when PIO_128_RX_MEM_RD32_DW1DW2 => -- mid sof MEM rd32
if ((i_axis_rx_tvalid) = '1') then
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
o_req_addr <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; -- only address (28:2) miss lsb 2 bits from PCIE protocal
o_req_compl <= '1' after TCQ;
o_req_compl_with_data <= '1' after TCQ;
o_wr_select <= "1000" after TCQ; -- ONLY BAR3?
state <= PIO_128_RX_WAIT_STATE after TCQ;
end if;
when PIO_128_RX_MEM_WR32_M_SOF => -- Middle SOF Second packet XX XX D0 H2
if (i_axis_rx_tuser(5) = '1') then -- BAR 3 OR (i_axis_rx_tuser(4) = '1') OR (i_axis_rx_tuser(5) = '1') then
if ((i_axis_rx_tvalid) = '1') then
--if ((i_axis_rx_tvalid) = '1') then
--if (wr_DW_cnt /= "000000000") then
wr_en <= '1' after TCQ;
o_wr_select <= "1000" after TCQ;
--wr_addr <= i_axis_rx_tdata(28 downto 2) & "0" after TCQ;
--*************************************************************************
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; -- try dw mx 300e always DW address in RX engine
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ; --ask pc to wait
state <= PIO_128_RX_WAIT_STATE after TCQ;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
elsif (i_axis_rx_tuser(4) = '1' and wr_DW_cnt_temp = "000000000") then -- BAR2 may write mulditple DW
if ((i_axis_rx_tvalid) = '1') then
if (wr_DW_cnt = "000000001") then
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) + wr_DW_cnt_temp after TCQ; --keep the same as old version 27
--if (wr_DW_cnt = 1) then
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) after TCQ;
-- elsif (wr_DW_cnt = 2) then
-- wr_data <= x"0000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) after TCQ;
-- elsif (wr_DW_cnt = 3) then
-- wr_data <= x"00000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
end if;
end if;
if (wr_DW_cnt > "000000001") then
wr_DW_cnt_temp <= wr_DW_cnt_temp + 1;
if (wr_DW_cnt_temp = "000000000" ) then
if ((i_axis_rx_tvalid) = '1') then
wr_data <= x"000000000000000000000000"
-- & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88)
& i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) after TCQ;
bar2_data_2dw <= i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) ;
end if; -- & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) after TCQ;
end if;
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) ;--keep the same as old version 27
--state <= PIO_128_RX_WAIT_STATE when (wr_DW_cnt = wr_DW_cnt +1 ) else PIO_128_RX_MEM_WR32_M_SOF ; --after TCQ;
end if;
elsif ( wr_DW_cnt = "000000010" and wr_DW_cnt_temp = "000000001") then -- BAR2 may write mulditple DW
wr_en <= '1' after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
wr_data <= x"000000000000000000000000" & bar2_data_2dw ;
wr_addr <= wr_addr + wr_DW_cnt_temp ;
state <= PIO_128_RX_WAIT_STATE;
-- end if;
elsif (i_axis_rx_tuser(3) = '1') then --BAR1
--if (wr_DW_cnt /= "000000000") then
wr_en <= '1' after TCQ;
o_wr_select <= "0010" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; --keep the same as old version 27
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) after TCQ;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
--end if;
elsif (i_axis_rx_tuser(2) = '1') then -- BAR 0 data more than 1DW goto next wr stage
if (wr_DW_cnt_alias_M <= "0000000011") then
wr_en <= '1' after TCQ;
o_wr_select <= "0001" after TCQ;
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; --keep the same as old version 27
wr_data <= i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & x"00000000" after TCQ; -- MASK SHOULD BE APPLIED LESS THAN 3
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
state <= PIO_128_RX_WAIT_STATE after TCQ;
elsif (wr_DW_cnt_alias_M > "0000000011") then
wr_en <= '0' after TCQ;
o_wr_select <= "0001" after TCQ;
--wr_DW_cnt <= i_axis_rx_tdata(9 downto 0);
wr_addr_temp <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; --keep the same as old version 27
wr_addr <= "00" & i_axis_rx_tdata(27 downto 2) after TCQ; --keep the same as old version 27
wr_data_temp <= --i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56)
--& i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88)
--& i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & x"00000000" after TCQ;
i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & x"00000000" after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_MEM_WR32_BAR0_MID after TCQ;
end if;
end if;
-- end if;
when PIO_128_RX_MEM_WR32_M_SOF_2 =>
if ((i_axis_rx_tvalid) = '1') then
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
--o_req_addr <= i_axis_rx_tdata(28 downto 2) after TCQ; -- only address (28:2) miss lsb 2 bits from PCIE protocal
wr_en <= '1' after TCQ;
--write_LASTBE
--write_1STBE
if (wr_DW_cnt <= 1) then
wr_mask <= write_LASTBE;
wr_DW_cnt <= wr_DW_cnt - 1;
wr_addr <= wr_addr + 1;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
elsif (wr_DW_cnt <= 2) then
--wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 2;
wr_addr <= wr_addr + 2;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
elsif (wr_DW_cnt <= 3) then
--wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 3;
wr_addr <= wr_addr + 3;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
else
wr_addr <= wr_addr + 4;
wr_DW_cnt <= wr_DW_cnt - 4;
end if;
end if;
--**
when PIO_128_RX_MEM_WR32_BAR0 => -- RIGHT SIDE SOF
-- if (i_axis_rx_tvalid = '1' OR axis_rx_tvalid = '1') then
if (i_axis_rx_tvalid = '1' ) then
wr_en <= '1' after TCQ;
wr_addr_temp <= wr_addr_temp + 4; -- DW address
wr_addr <= wr_addr_temp;
wr_DW_cnt <= wr_DW_cnt - 4;
wr_data_temp <= i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & x"000000000000000000000000" after TCQ;
wr_data <= --i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120)
i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(127 downto 96);
--wr_data <= i_axis_rx_tdata(127 downto 0) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ; -- if '1' not busy if 0 busy
if (wr_DW_cnt <= 1) then
wr_mask <= write_LASTBE;
wr_DW_cnt <= wr_DW_cnt - 1;
wr_addr <= wr_addr + 1;
wr_en <= '1';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ; --wait for write finished
elsif (wr_DW_cnt <= 2) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 2;
wr_addr <= wr_addr + 2;
wr_en <= '1';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
elsif (wr_DW_cnt <= 3) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 3;
wr_addr <= wr_addr + 3;
wr_en <= '1';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
elsif (wr_DW_cnt = 4) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 3;
wr_addr <= wr_addr + 3;
wr_en <= '1';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
end if;
else
state <= PIO_128_RX_MEM_WR32_BAR0 after TCQ;
end if;
when PIO_128_RX_MEM_WR32_BAR0_MID => -- MID SOF
if (i_axis_rx_tvalid = '1' OR axis_rx_tvalid = '1') then
--wr_en_mid_d <= '1' after TCQ;
wr_en <= '1' after TCQ;
if wr_en = '1' then
wr_addr_temp <= wr_addr_temp + 4; -- DW address
wr_addr <= wr_addr_temp;
wr_DW_cnt <= wr_DW_cnt - 4;
end if;
wr_data_temp <= i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & x"00000000" after TCQ;
wr_data <= i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(127 downto 32);
--wr_data <= i_axis_rx_tdata(127 downto 0) after TCQ;
o_axis_rx_tready_v6pcie0 <= '1' after TCQ; -- if '1' not busy if 0 busy
if (wr_DW_cnt <= 1) then
wr_mask <= write_LASTBE;
wr_DW_cnt <= wr_DW_cnt - 1;
wr_addr <= wr_addr + 1;
wr_en <= '0';
wr_en_mid_d <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ; --wait for write finished
elsif (wr_DW_cnt <= 2) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 2;
wr_addr <= wr_addr + 2;
wr_en <= '0';
wr_en_mid_d <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
elsif (wr_DW_cnt <= 3) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 3;
wr_addr <= wr_addr + 3;
wr_en <= '0';
wr_en_mid_d <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
elsif (wr_DW_cnt = 4) then
-- wr_mask <= wr_be(7 downto 4);
wr_DW_cnt <= wr_DW_cnt - 4;
wr_addr <= wr_addr + 4;
wr_en <= '0';
wr_en_mid_d <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0' after TCQ;
end if;
else
state <= PIO_128_RX_MEM_WR32_BAR0_MID after TCQ;
end if;
when PIO_128_RX_MEM_WR32_BAR2 => -- RIGHT SIDE SOF
debug_rx_state <= "0001";
if ((i_axis_rx_tvalid) = '1') then
--if (wr_DW_cnt /= "000000000") then -- 2 DW
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
wr_addr <= wr_addr + 1; -- BAR2 fifo each entry is 4 byte
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) after TCQ;
--o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
-- state <= PIO_128_RX_MEM_WR32_BAR2 after TCQ;
--end if;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
when PIO_128_RX_MEM_WR32_BAR2_MID => -- RIGHT SIDE SOF
if ((i_axis_rx_tvalid) = '1') then
--if (wr_DW_cnt /= "000000000") then -- 2 DW
wr_en <= '1' after TCQ;
o_wr_select <= "0100" after TCQ;
wr_addr <= wr_addr + 1; -- BAR2 fifo each entry is 4 byte
wr_data <= wr_data_temp;
--o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
-- state <= PIO_128_RX_MEM_WR32_BAR2 after TCQ;
--end if;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
--** DMA state
when PIO_DMA_RX_CPLD_CHK_DMA_R_SOF => -- wait for tag match
debug_rx_state <= "0100";
o_axis_rx_tready_v6pcie0 <= '0';
cpld_tag_valid <= '0';
--if (i_axis_rx_tvalid = '1') then
--wr_data_temp <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120);
-- --wr_data <= i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(31 downto 0);
--end if;
--if cpld_tag_valid = '1' then
if srv_tag_match = '1' then
DMA_wr_addr <= srv_DMA_wr_addr;
wr_addr <= srv_DMA_wr_addr;
--DMA_wr_DW_cnt <= srv_DMA_wr_DW_cnt;
--cpld_tag_valid <= '0';
--o_axis_rx_tready_v6pcie0 <= '1';
if (srv_DMA_wr_DW_cnt = 1) then -- just 1 DW response -- -- D0 H2
wr_mask <= "0010";
o_wr_select <= "0001";
wr_en <= '1' after TCQ;
wr_data <= wr_data_temp;
wr_addr <= wr_addr + 1;
wr_DW_cnt <= srv_DMA_wr_DW_cnt - 1;
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0'; -- stop
else -- Has more DW continue wirte in next stage
o_axis_rx_tready_v6pcie0 <= '1'; -- receiving next packet
wr_mask <= "1111"; -- *D3D2D1D0
o_wr_select <= "0001"; -- select bar0
wr_en <= '0' after TCQ;
--wr_data <= wr_data_temp;
--wr_addr <= wr_addr + 4;
--wr_DW_cnt <= srv_DMA_wr_DW_cnt - 4;
--DMA_wr_DW_cnt <= srv_DMA_wr_DW_cnt;
state <= PIO_DMA_RX_CPLD_WR_R_SOF;
end if;
elsif srv_error_DW_cnt = '1' then
o_ERROR_CPLD_state <= "01";
o_ERROR_DMA_WR_CNT <= '1';
o_Error_hdr_strobe2 <= '1';
o_Error_hdr_strobe1 <= '1'; -- save header 0,1 also
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
--cpld_tag_valid <= '0';
state <= PIO_DMA_RX_CPLD_ERROR;
elsif srv_error_TAG_No_Match = '1' then
o_ERROR_DMA_TAG <= '1';
o_ERROR_DMA_CPLD_tag <= cpl_TAG(4 downto 0); -- the tag is from the input header, not from the DMA controller
o_Error_hdr_strobe2 <= '1';
o_Error_hdr_strobe1 <= '1'; -- save header 0,1 also
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
--cpld_tag_valid <= '0';
state <= PIO_DMA_RX_CPLD_ERROR;
end if;
-- 00000008_4A000002_00000000_00000000
-- 00000000_2211008_7766554433_01000020 <=
when PIO_DMA_RX_CPLD_CHK_DMA => -- *Only for Mid sof D2D1D0H2
if (i_axis_rx_tvalid = '1') then
o_Header_DW2 <= i_axis_rx_tdata(31 downto 0); -- save header, DW2
--cpld_tag_valid <= i_axis_rx_tvalid;
o_axis_rx_tready_v6pcie0 <= '0';
cpl_TAG <= i_axis_rx_tdata(15 downto 8); -- H2
cpld_tag_valid <= '1';
end if;
--if cpld_tag_valid = '1' then REMOVE TAG VALID -Ting timming independent
-- wait for DMA_CPLD_service
if srv_tag_match = '1' then
cpld_tag_valid <= '0';
DMA_wr_addr <= srv_DMA_wr_addr;
wr_addr <= srv_DMA_wr_addr;
DMA_wr_DW_cnt <= srv_DMA_wr_DW_cnt;
--cpld_tag_valid <= '0';
o_axis_rx_tready_v6pcie0 <= '1';
wr_en <= '0' after TCQ;
if (DMA_wr_DW_cnt = 1) then -- just 1 DW response -- -- D0 H2
wr_mask <= "0010";
o_wr_select <= "0001";
wr_en <= '1' after TCQ;
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 1;
wr_DW_cnt <= wr_DW_cnt - 1;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
elsif (DMA_wr_DW_cnt = 2) then -- just 2 DW response -- D1 D0 H2
wr_mask <= "0110";
o_wr_select <= "0001";
wr_en <= '1' after TCQ;
wr_data <= x"0000000000000000" & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 2;
wr_DW_cnt <= wr_DW_cnt - 2;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
elsif (DMA_wr_DW_cnt = 3) then -- just 3 DW response -- D2 D1 D0 H2
wr_mask <= "1110";
o_wr_select <= "0001";
wr_en <= '1' after TCQ;
wr_data <= x"00000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 3;
wr_DW_cnt <= wr_DW_cnt - 3;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
else -- Has more DW continue wirte in next stage
wr_mask <= "0000"; -- *D2D1D0H2
o_wr_select <= "0001"; -- select bar0
wr_en <= '0' after TCQ; -- test it may be good timing wr early one cycle
wr_data_temp <= i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & x"00000000"; -- mask H2 32 bits
--wr_addr <= wr_addr + 3;
--wr_DW_cnt <= wr_DW_cnt - 3;
state <= PIO_DMA_RX_CPLD;
end if;
elsif srv_error_DW_cnt = '1' then
o_ERROR_CPLD_state <= "01";
o_ERROR_DMA_WR_CNT <= '1';
o_Error_hdr_strobe2 <= '1';
o_Error_hdr_strobe1 <= '1'; -- save header 0,1 also
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
--cpld_tag_valid <= '0';
state <= PIO_DMA_RX_CPLD_ERROR;
elsif srv_error_TAG_No_Match = '1' then
o_ERROR_DMA_TAG <= '1';
o_ERROR_DMA_CPLD_tag <= cpl_TAG(4 downto 0); -- the tag is from the input header, not from the DMA controller
o_Error_hdr_strobe2 <= '1';
o_Error_hdr_strobe1 <= '1'; -- save header 0,1 also
o_cfg_err_cpl_unexpect <= '1';
o_cfg_err_posted <= '1';
--cpld_tag_valid <= '0';
state <= PIO_DMA_RX_CPLD_ERROR;
end if;
--end if;
when PIO_DMA_RX_CPLD =>
if (i_axis_rx_tvalid = '1') then
o_wr_select <= "0001"; -- DMA write to BAR0 only
wr_be <= (others => '1');
wr_data_temp <= x"00000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_data <= wr_data_temp(95 downto 0) & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24);
wr_en <= '1';
wr_addr <= wr_addr + 4;
wr_DW_cnt <= wr_DW_cnt - 4;
o_axis_rx_tready_v6pcie0 <= '1';
--
if wr_DW_cnt = 0 then --DMA write is finished
o_axis_rx_tready_v6pcie0 <= '0'; -- i_axis_rx_tlast should be active but NOT acknowledged yet
state <= PIO_128_RX_WAIT_STATE;
else
--if wr_DW_cnt <= 4 then -- last DW ?
if (DMA_wr_DW_cnt = 1) then -- just 1 DW response -- -- D0 H2
wr_mask <= "0010";
--o_wr_select <= "0001";
--wr_en <= '1' after TCQ;
wr_data <= x"000000000000000000000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 1;
wr_DW_cnt <= wr_DW_cnt - 1;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
elsif (DMA_wr_DW_cnt = 2) then -- just 2 DW response -- D1 D0 H2
wr_mask <= "0110";
--o_wr_select <= "0001";
--wr_en <= '1' after TCQ;
wr_data <= x"0000000000000000" & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 2;
wr_DW_cnt <= wr_DW_cnt - 2;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
elsif (DMA_wr_DW_cnt = 3) then -- just 3 DW response -- D2 D1 D0 H2
wr_mask <= "1110";
--o_wr_select <= "0001";
--wr_en <= '1' after TCQ;
wr_data <= x"00000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120) & i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56);
wr_addr <= wr_addr + 3;
wr_DW_cnt <= wr_DW_cnt - 3;
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_128_RX_WAIT_STATE;
end if;
--end if;
end if;
end if;
when PIO_DMA_RX_CPLD_WR_R_SOF => -- BAR0 write DMA WRITE
--
debug_rx_state <= "0010";
if (i_axis_rx_tvalid = '1') then -- one cycle delay since first packet has 1 DW waiting for cnt one cycle
o_wr_select <= "0001"; -- DMA write to BAR0 only
wr_be <= (others => '1');
wr_data_temp <= x"000000000000000000000000" & i_axis_rx_tdata(103 downto 96) & i_axis_rx_tdata(111 downto 104) & i_axis_rx_tdata(119 downto 112) & i_axis_rx_tdata(127 downto 120);
wr_data <= i_axis_rx_tdata(71 downto 64) & i_axis_rx_tdata(79 downto 72) & i_axis_rx_tdata(87 downto 80) & i_axis_rx_tdata(95 downto 88) & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(31 downto 0);
wr_en <= '1';
wr_addr <= wr_addr + 4;
wr_DW_cnt <= wr_DW_cnt - 4;
o_wr_mask <= "0000000000000000";
o_axis_rx_tready_v6pcie0 <= '1';
--
if wr_DW_cnt = 4 then --DMA write is finished
o_axis_rx_tready_v6pcie0 <= '0'; -- i_axis_rx_tlast should be active but NOT acknowledged yet
--o_wr_select <= "0000";
--wr_en <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
else
--if wr_DW_cnt < 4 then -- last DW ?
if wr_DW_cnt = 3 then
wr_addr <= wr_addr + 3;
wr_DW_cnt <= wr_DW_cnt - 3;
wr_data <= x"00000000" & i_axis_rx_tdata(39 downto 32) & i_axis_rx_tdata(47 downto 40) & i_axis_rx_tdata(55 downto 48) & i_axis_rx_tdata(63 downto 56) & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(31 downto 0);
o_wr_mask <= "1111000000000000";
o_axis_rx_tready_v6pcie0 <= '0'; -- i_axis_rx_tlast should be active but NOT acknowledged yet
-- wr_en <= '0';
-- o_wr_select <= "0000";
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
if wr_DW_cnt = 2 then
wr_addr <= wr_addr + 2;
wr_DW_cnt <= wr_DW_cnt - 2;
wr_data <= x"0000000000000000" & i_axis_rx_tdata(7 downto 0) & i_axis_rx_tdata(15 downto 8) & i_axis_rx_tdata(23 downto 16) & i_axis_rx_tdata(31 downto 24) & wr_data_temp(31 downto 0);
o_wr_mask <= "1111111100000000";
o_axis_rx_tready_v6pcie0 <= '0'; -- i_axis_rx_tlast should be active but NOT acknowledged yet
-- o_wr_select <= "0000";
-- wr_en <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
if wr_DW_cnt = 1 then
wr_addr <= wr_addr + 1;
wr_DW_cnt <= wr_DW_cnt - 1;
wr_data <= x"000000000000000000000000" & wr_data_temp(31 downto 0);
o_wr_mask <= "1111111111110000";
o_axis_rx_tready_v6pcie0 <= '0'; -- i_axis_rx_tlast should be active but NOT acknowledged yet
-- o_wr_select <= "0000";
-- wr_en <= '0';
state <= PIO_128_RX_WAIT_STATE;
o_axis_rx_tready_v6pcie0 <= '0';
end if;
--end if;
end if;
end if;
when PIO_DMA_RX_CPL_ERROR => -- axis_rx_tready should be '1', error detected from header DW01
o_axis_rx_tready_v6pcie0 <= '1';
if (i_axis_rx_tvalid = '1' and o_axis_rx_tready_v6pcie0 = '1') then -- i_axis_rx_tlast should be active
--if use_1stBE = '1' then
-- use_1stBE <= '0';
-- o_Header_DW2 <= i_axis_rx_tdata(31 downto 0); -- save header, DW2
-- o_Error_hdr_strobe2 <= '1';
-- o_Error_hdr_strobe1 <= '1'; -- save header 0,1 also
--end if;
if i_axis_rx_tlast = '1' then
axis_rx_tready <= '0';
state <= PIO_DMA_RX_CPL_ERROR_2;
end if;
end if;
when PIO_DMA_RX_CPL_ERROR_2 =>
o_DMA_wr_error <= '1';
if DMA_wr_active = '0' then
axis_rx_tready <= '1';
state <= PIO_128_RX_RST_STATE;
end if;
when PIO_DMA_RX_CPLD_ERROR => -- axis_rx_tready should be '0', error detected from header DW2
o_axis_rx_tready_v6pcie0 <= '1';
if i_axis_rx_tvalid = '1' and i_axis_rx_tlast = '1' and o_axis_rx_tready_v6pcie0 = '1' then
o_axis_rx_tready_v6pcie0 <= '0';
state <= PIO_DMA_RX_CPLD_ERROR_2;
end if;
when PIO_DMA_RX_CPLD_ERROR_2 =>
o_DMA_wr_error <= '1';
if DMA_wr_active = '0' then
axis_rx_tready <= '1';
state <= PIO_128_RX_RST_STATE;
end if;
when PIO_128_RX_WAIT_STATE =>
debug_rx_state <= "0011";
--wait_state_time_out_cnt <= wait_state_time_out_cnt + 1;
-- wr_busy for BAR 123 if barhit is active wr_busy is active
wr_en <= '0' after TCQ;
--wr_be <= "0000" after TCQ;
o_wr_select <= "0000" after TCQ;
--o_req_compl <= '1' after TCQ;
single_DW_end <= '0';
two_DW_end <= '0';
three_DW_end <= '0';
o_axis_rx_tready_v6pcie0 <= '0';
if ((tlp_type = RX_MEM_WR32_FMT_TYPE) and (not wr_busy) = '1') then
use_1stBE <= '1';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_RST_STATE after TCQ;
BAR_hit <= (others => '0');
o_req_compl <= '0' after TCQ;
--o_wr_be <= (others => '0');
elsif ((tlp_type = RX_MEM_WR64_FMT_TYPE) and (not wr_busy) = '1') then
use_1stBE <= '1';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_RST_STATE after TCQ;
BAR_hit <= (others => '0');
o_req_compl <= '0' after TCQ;
--o_wr_be <= (others => '0');
elsif ((tlp_type = RX_MEM_RD32_FMT_TYPE) and (i_compl_done = '1')) then
use_1stBE <= '1';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_RST_STATE after TCQ;
BAR_hit <= (others => '0');
o_req_compl <= '0' after TCQ;
o_req_compl_with_data <= '0' after TCQ;
--o_wr_be <= (others => '0');
elsif ((tlp_type = RX_MEM_RD64_FMT_TYPE) and (i_compl_done = '1')) then
use_1stBE <= '1';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
state <= PIO_128_RX_RST_STATE after TCQ;
BAR_hit <= (others => '0');
o_req_compl <= '0' after TCQ;
--o_wr_be <= (others => '0');
elsif ((tlp_type = RX_CPLD_FMT_TYPE) and (not wr_busy) = '1') then
use_1stBE <= '1';
DMA_timeout_cnt_en <= '0';
o_axis_rx_tready_v6pcie0 <= '1' after TCQ;
o_wr_mask <= "0000000000000000"; -- 0 can be write to
state <= PIO_128_RX_RST_STATE after TCQ;
--o_wr_be <= (others => '0');
else
--BAR_hit <= (others=> '0');
state <= PIO_128_RX_WAIT_STATE after TCQ;
end if; --`PIO_128_RX_WAIT_STATE : begin
--when DELAY_ONE_CYCLE =>
-- state <= PIO_128_RX_RST_STATE after TCQ;
when others => state <= PIO_128_RX_RST_STATE after TCQ;
end case;
end if;
end process;
end rtl; -- PIO_RX_ENGINE
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