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查看: 2746|回复: 8

[招聘] 【Marvell招聘】ASIC Design/DFT/Implementation工程师

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发表于 2014-12-29 13:19:10 | 显示全部楼层 |阅读模式

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1Job Title:SoC asic Engineer

Department: Cellular Engineering
Location: Shanghai/Beijing/Chengdu


Job Description: modem:
3G: TD-SCDMA and WCDMA modem development
4G: TD-LTE modem development
SoC: next generation cellphone SoC full design cycle from spec.to massproduction.
Largest chip inside Marvell.
1) R&D L2/L3 of the above protocol stacks.
2)Integration and Testing with the UE system.

Qualification:
MS degree in microelectronics, or electrical engineering.
At least three years working experience.
Experience in real design projects (front-end or backend) is a strongplus.
Good team work spirit and communication skill. Eager to learn, work and grow ina challenging project.


2Job Title: ASIC Implementation Engineer

Location: Shanghai/Beijing

Job Description:

- Block, IP macro or SoC level implementation in 28nm or20nm TSMC/UMC process

- UPF Synthesis with Synopsys DC or DCT/G flows

- RTL2Gate and Gate2Gate formal check with LEC and/orformality tools.

- Working with BE team to timing closure in Primetime-SIon multi-corners and multi-modes

-
Ability tobuild or perfect the EDA-methodology-flow with perl, tcl or shell

- Knowledge on DFT (mbist/scan)will be an added advantage


Qualifications:

- BSEE degree or above

- Strong understanding of synthesis flowusing DC/DCT/DCG - for a low power (UPF) and high speed- complex SoC

- Hands on experience with formalverification tools such as LEC and/or formality

- Must have the CTS conceptions in ICC atP&R stage
- Strong STA skills. Must have thorough knowledge on closing timing at unit andtop level

- Experience in mbist and scan will be plus

- Proficient in Perl, Tcl and Shellprogramming

-Good team work spirit

3Job Title: ASIC DFT design Engineer

Location: Shanghai/Beijing

Job Description:

-Block, IPand SoC level DFT implementation (JTAG, Scan, Mbist and Analog/IP test etc.)and RTL integration;

-Participatein test spec/plan definition; create the DFT design document and signoffDFT review checklists;

-Testpatterns/vectors generation and verification;

-Interfaceto backend team on physical design and timing closure;

-Interfaceto test engineers on ATE and vectors bring-up and debugging;

-Chip DFTquality sign-off

-DFT STA,constraint generation, formal and timing closure


Qualifications:

- DFT design and integration experience

- Hands on DFT implementation experience (Bscan, Mbist, DC/AC Scan, analogIP test circuit integration, IDDQ test, ATPG and test pattern verification)

- Expertise with DFT tools from Synopsy, Mentor, Syntest etc.

- Strong logic design and verification background

- Experience in Synthesis and STA will be plus

- Proficient in Perl, tcl and shell programming

- BSEE degree or above

- Good team work spirit

If you are interested in the position, please send your resume to the following email address:   jiangrr@marvell.com

Subject of your email should be: School_Name_Applied position_Information source
Eg.SJTU_Zhang Peng _Data Analyst_BBS

发表于 2014-12-29 14:48:53 | 显示全部楼层
一年半工作经验可以吗?
 楼主| 发表于 2014-12-29 17:29:47 | 显示全部楼层
回复 2# wolf46


   你好!我们都可以看看的。你可以先将简历发过来,如果合适,我们会和你做进一步沟通!
发表于 2014-12-30 10:01:51 | 显示全部楼层
回复 1# Hwangbo


junior的职位?
 楼主| 发表于 2014-12-30 13:38:58 | 显示全部楼层
回复 4# ccchunyu2652


   我们Junior和senior都是有的,主要还是看候选人的工作经验已经自身的背景!
发表于 2014-12-31 16:05:13 | 显示全部楼层
DFT的是junior职位吗?招几个人呀?我想试试。LZ是HR吗?
 楼主| 发表于 2014-12-31 17:00:39 | 显示全部楼层
回复 6# xiaoxuelovepig


   你好!我们职位的level是根据候选人的背景还有工作经历给出的~我是HR,没错!你如果感兴趣可以投递简历到相应的邮箱哦!
发表于 2018-4-13 07:26:02 | 显示全部楼层
Thanks for sharing!
发表于 2018-11-12 15:20:45 | 显示全部楼层
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