芯得芯case 海外

jj_seu

芯得芯CASE（海外）

[url=mailto:简历发ic@hi-talent.com]简历发ic@hi-talent.com[/url]

Please find details below.
Job Type - Permanent.
Job Location - Bangalore.
Company - Fast growing serviced based Semiconductor Company.
Salary - Not a constrain for the right candidate.

We are looking for a sr. candidate with 12Yrs years of experience in IP/ SoC/asic Design & Verification.

Apart from the above position we also have below 4 other req. kindly send usyour updated profile if your profile suites any of these.

1. IP Design:
An IP Design Engineer with the following qualifications is required:
4+ Years of experience in complex IP and sub-system design.
Familiar with various arm protocols - AXI, AHB, APB etc.li>
Power management implementation, synchronous/asynchronous clocking and resetscheme.
Knowledge of design concepts for high frequency operations is preferred.
Familiar with various Design Quality checks.
Knowledge of memory and cache based designs is preferable.

2. Design Verification:
The Following are the qualifications for a SoC RTL Design Engineer:
3+ Years of experience in Complex SoC Integration
Should have knowledge ARM protocols - AXI, AHB, APB etc.
Familiar with various Design Quality checks
Basic Power Management concepts and implementation.
Understanding of synthesis and design constraints is preferable.

3. IP Verification,
For the position of IP Verification Engineer the following qualifications mustbe met:
4+ years of experience on IP Verification.
Developed the test benches using the System verilog, UVM or Specman/eRM.
Developed the BFM/VIP using System Verilog or UVM.
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage and Codegoals.
Understanding of Cache Concepts is desirable.

4. SOC Verification:
We are looking for a SoC Verification Engineer With The FollowingQualifications:
3+ years of experience on SoC Verification
Developed the test benches using the System Verilog and UVM.
Knowledge of C-based Verification is preferred
Should able to create Verification plan and Test Plan.
Write and execute the test cases to meet the functional coverage goals.
Working knowledge of Power Aware RTL and Gate Level Simulation.
Understanding of ARM Core and DDR/LPDDR is preferable.
PCIe, USB, Serial Peripheral knowledge is preferred.

Also let us know below details while sending your profile:-
Reason for job change –
Current CTC –
Expected CTC –
Notice Period –

We also have opening for Back-endDesign (Physical Design, STA Synthesis, DFT).

Analog Design/ layout, Memory Layout/ Design, std cell design/ layout.

Webasically deal with Semiconductor companies hence if you would like to exploresome opportunities please send us your profile.

Thanks & Kind Regards

Best Regards

Jane.Jin金娟

Principal Consultant & General Manager @ Hi-Talent Consulting Co.,Ltd.

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E-Mail:    Jane-Jin@hi-talent.com

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arthur_wang_orz

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enemyatgates

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