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[求助] Altera FPGA程序封装

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发表于 2014-11-27 13:20:51 | 显示全部楼层 |阅读模式

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看过一些资料Xilinx的FPGA好像可以将程序封装成类似IP核或网表形式,不知道Altera的FPGA可以不?这个到底能否实现,或是那里有参考文献,给个链接,学习一下。
     谢谢!
发表于 2014-12-31 09:06:55 | 显示全部楼层
有 自行百度QXP或VQM
发表于 2014-12-31 09:11:26 | 显示全部楼层
Verilog Quartus Mapping File (.vqm) Definition
An ASCII text file (with the extension .vqm) that contains an node-level (or atom) netlist. VQM files are typically generated by EDA synthesis tools such as Synplicity Synplify, and contain the logid for the design.
A VQM file can also be generated by the Quartus II Compiler in order to save synthesis results for the LogicLock Import / Export flow in one of the following ways:
Turn on Save a node-level netlist in the Compilation Process Settings page in the Settings dialog box, and then compile the design.
Turn on Save a node-level netlist in the Back-Annotate Assignments dialog box and back-annotate a design.
Click Start VQM Writer.
Altera recommends using the Incremental Compilation flow to preserve synthesis and fitting results in preference to the LogicLock Import / Export flow or back-annotation flow.
When generated from intermediate synthesis results in the Quartus II software, the VQM File is placed in the <project directory>\atom_netlists\ directory. You can then use the VQM File by creating and then compiling a new project from the file.
Altera recommends that you do not edit VQM Files.
发表于 2014-12-31 09:35:21 | 显示全部楼层
好资料,顶顶顶
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