为什么不能产生网表文件，SDF，SDC文件？

ICSYS · 发表于 2014-5-16 18:59:25

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本帖最后由 ICSYS 于 2014-5-18 21:12 编辑

我用 write -format verilog -hierarchy -output file.v    write_sdf  -version 2.1 /home/pro/syn/sdf/file.sdf
   write_sdc  /home/pro/sdc/file.sdc
命令无法产生网表和SDF SDC 文件，顺便，产生.db文件干吗用？
有高手清楚的话不吝指教哈~谢谢了哈~===========================================
我用 write -format verilog -hierarchy -output file.v    write_sdf  -version 2.1 /home/project/syn/sdf/file.sdf
   write_sdc  /home/project/sdc/file.sdc
命令无法产生网表和SDF SDC 文件，顺便，产生.db文件干吗用？
有高手清楚的话不吝指教哈~谢谢了哈~
主要问题如下；
warning： can't find the design PS_IBUF...
warning： can't find the design PS_OBUF...
(这两个buffer是设计代码里在输入输出端口上加的buffer)
warning： design 'design_core' has '2' unresolved references...

第二个疑问是；log里的提示。。。
linking design ‘design_core'
using the following design and libraries...
design_core          /home/project/syn/src/design_core.db

我搞不懂的是我的src下面只有.v设计文件，怎么产生了
design_core.db库文件呢？而且我设置过综合的target_library是DC目录下synopsys的库，怎么产生了上面那个design_core.db库呢？请大侠们指教啊...

==================================log===================
read_file -format verilog {/home/project/syn/src/design_core.v}
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/gtech.db'
Loading db file '/eda/synopsys/dc2008_09/libraries/syn/standard.sldb'
  Loading link library 'gtech'
Loading verilog file '/home/project/syn/src/design_core.v'
Detecting input file type automatically (-rtl or -netlist).
Running DC verilog reader
Reading with Presto hdl Compiler (equivalent to -rtl option).
Running PRESTO HDLC
Compiling source file /home/project/syn/src/design_core.v==================================================
set_driving_cell -lib_cell PS_IBUF -pin Z [all_inputs]
Warning: Design 'design_core' has '2' unresolved references. For more detailed information, use the "link" command. (UID-341)
Error: Cannot find the specified driving cell in memory. (UID-993)