每日一奖----20140508

damonzhao

Q3. Why clock is not synthesized in DC?

leolf

Clock need accuracy delay time of cell and wire load. In Synthesis procedure, it only transfer the RTL Verilog to gate level Verilog. The wile load mode and standard cell delay timing is still not accuracy enough for real clock skew calculation.
So, normally will put the clock synthesis into Auto Place & Route procedure to handle. If it's only a simply local small area clock. U can also fix the setup/hold time in synthesis because it's low risk.

jinwei91

1)cts needs accurate logic cell location after place_opt; 2)ICC has accurate physical information than DC; 3)etc.  waiting for others' answer....

zero_0

Agree "jinwei91".
The RC calculated from WLM in DC is so different than real RC, so synthesizing clock is no sense wasting time.
If we use this synthesized data to optimize clock tree after placement, it may increase the complexity of clock trees, chip size and power consumption.

stheng

The main purpose of synthesis is to do logic mapping and optimization, under assumption of ideal clock network.  Since the floorplan and all the other physical info is not compulsory in synthesis stage, and hence the instances are not placed, it is better not to touch the clock network.

mnluan

哈哈，是不是这题太简单了，所以大家都在秀英文呢。。我来给个中文的答案。方便英文如我一般差的同学。因为DC算不准时钟树的延时。不知道reg的具体位置，时钟具体用哪些层连线。

换个思路来回答，因为时钟树是后端干的活，咱不能抢了人家的工作量。哈哈。玩笑了。

damonzhao

其实这道题就是问：什么是CTS？可以和RTL逻辑综合一起完成么？