Computer Architecture Complexity And Correctness Risc Design

leasor · 发表于 2014-3-24 07:28:55

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Computer Architecture Complexity And Correctness Risc Design
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N THIS BOOK we develop at the gate level the complete design of a
pipelined RISC processor with delayed branch, forwarding, hardware
interlock, precise maskable nested interrupts, caches, and a fully IEEE-
compliant floating point unit. The design is completely modular. This
permits us to give rigorous correctness proofs for almost every part of the
design. Also, because we can compute gate counts and gate delays, we can
formally analyze the cost effectiveness of all parts of the design.

Computer Architecture Complexity And Correctness Risc Design.pdf (2.6 MB, 下载次数: 350 )