谱瑞集成电路(上海) digital/logic verification engineer

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职位：Digital Verification Engineer
RESPONSIBILITIES:
- Develop and execute verification plan
- Develop and maintain verification environment from unit level to system level
- Define and implement functional/code coverage plan
- Code/functional coverage analysis
- Responsible for running both RTL & gate level simulation
- Develop testing and regression methodologies for new verification flow
- Develop/maintain/enhance environment tools/scripts/makefiles

REQUIREMENTS:
- Familiar with hardware verification language(Vera, Specman-E, SystemC, Systemverilog), SystemVerilog is a strong plus -  Experience in UVM is preferred
- Proficient and experienced with the C/C++ program
- Experience in asic design or verification
- Proficient with Verilog hdl - Proficient with one or more scripting languages, such as Shell, Perl and TCL
- Familiar with logic simulators and debug tools (VCS, NC-Verilog, Verdi etc) - Master degree in Electrical Engineering/Computer

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