各位大神,请留步啊
本人初学FPGA,拼接了一个verilog小程序,实现的功能是从串口发送数据到FPGA内部存储器,然后再从内部存储器读取数据到串口,在modelsim上跑通了,可是到了板子上出现了问题,现在问题是这样的,RTL-simulation没问题,Gate-Level Simulation跑不通,提示有
Critical Warning (332148): Timing requirements not met
Info (11105): For recommendations on closing timing, run Report Timing Closure Recommendations in the TimeQuest Timing Analyzer.
Critical Warning (332012): Synopsys Design Constraints File file not found: 'uart_i2c.sdc'. A Synopsys Design Constraints File is required by the TimeQuest Timing Analyzer to get proper timing constraints. Without it, the Compiler will not properly optimize the design.
谁能帮我调试下,告诉我是什么原因,实在是没脾气了,求指教啊
还有这个网站真的不错