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[原创] Systemverilog for Design and Verification Using UVM

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发表于 2013-6-8 21:14:03 | 显示全部楼层 |阅读模式

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Systemverilog for Design and Verification using UVM
From RTL to Synthesis

Azadpour, Mark A.

2013, 300p. 100 illus..


Available Formats:
Provides a practical guide to the use of SystemVerilog for both design and verification, unlike any other book currently available
  • Uses the Universal Verification Methodology (UVM) to build test-benches, in a manner accessible to novices
  • Covers the practical essentials needed for design, verification, synthesis and static timing analysis, which readers might otherwise have to find in several books
This book is an “A-Z” guide to using SystemVerilog for asic design, from conception to RTL coding, to synthesis and verification.  Readers will benefit from a thorough introduction to the powerful constructs and features of SystemVerilog. In addition, the verification methodology of Universal Verification Methodology (UVM) is used to build test-benches that allow for verification of complicated designs and synthesis basics are discussed, using the Synopsys Design Compiler (DC).  To complete this book’s package as a practical guide, readers are introduced to the fundamentals of static timing analysis.

Content Level » Professional/practitioner
Keywords » ASIC Design - ASIC Verification - SystemVerilog - SystemVerilog for Design - SystemVerilog for Verification - UVM - Universal Verification Methodology - VLSI Verification
 楼主| 发表于 2013-6-8 21:14:51 | 显示全部楼层
回复 1# baddy2323


   暂时没有pdf版本
发表于 2013-6-8 22:45:27 | 显示全部楼层
sigh,没书啊,
白激动了。。。
发表于 2013-6-11 21:35:28 | 显示全部楼层
楼主怎么没有附件啊?
发表于 2013-6-12 15:24:25 | 显示全部楼层
回复 1# baddy2323


    标题党,很可恨啊
发表于 2013-6-12 22:55:15 | 显示全部楼层
Thanks a lot
发表于 2013-7-5 23:15:26 | 显示全部楼层
没pdf确实好可惜啊
发表于 2013-7-7 19:11:18 | 显示全部楼层
Hao Shu
发表于 2013-7-26 09:41:27 | 显示全部楼层
坐等啊
发表于 2013-10-3 23:06:57 | 显示全部楼层
同坐等~
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