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Digital_Logic_Testing_And_Simulation_MAZ
This textbook contains 12 chapters. The first six chapters can be viewed as building
blocks. Topics covered include simulation, fault simulation, combinational and
sequential test pattern generation, and a brief introduction to tester architectures.
The last six chapters build on the first six. They cover design-for-test (DFT), built-in
self-test (BIST), fault tolerance, memory test,
and, finally, behavioral test
and verification. This dichotomy represents a natural partition for a two-semester
course. Some examples make use of the verilog hardware design language (hdl).
For those readers who do not have access to a commercial Verilog product, a quite
good (and free) Verilog compiler/simulator can be downloaded from http://
www.icarus.com. Every effort was made to avoid relying on advanced HDL concepts,
so that the student familiar only with programming languages, such as C, can
follow the Verilog examples.
A JOHN WILEY & SONS, INC., PUBLICATION
[ 本帖最后由 jason99pan 于 2006-12-31 04:58 编辑 ] |
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发表于 2006-12-28 04:43:30
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