SystemVerilog Verification UVM 1.1 Student & Lab Guide 2011.12（可搜寻 PDF）

ALUOp · 发表于 2012-10-26 10:00:10

马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。

您需要登录才可以下载或查看，没有账号？注册

x

本帖最后由 ALUOp 于 2012-11-15 15:32 编辑

Systemverilog Verification UVM 1.1 Student & Lab Guide 2011.12（可搜寻 PDF）

At the end of this workshop the student should be able to:

Develop UVM 1.1 tests
Implement and manage report messages for printing to terminal or file
Create random stimulus and sequences
Build and manage stimulus sequencers, drivers and monitors
Create configurable agents containing sequencer, driver and monitor for re-use
Create and manage configurable environments including agents, scoreboards, TLM ports and functional coverage objects
Implement a collection of testcases each targeting a corner case of interest
Create an abstraction of DUT registers and manage these registers during test