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[求助] 关于create_clock和create_generate_clock问题?

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发表于 2012-9-26 19:47:18 | 显示全部楼层 |阅读模式

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大家好,想问一下,如图所示,对于gen_clk这个分频时钟,用create_clock和create_generate_clock定义,有什么区别?谢谢!
div2.bmp
发表于 2012-9-26 20:44:48 | 显示全部楼层
做cts的时候有区别
 楼主| 发表于 2012-9-26 21:49:10 | 显示全部楼层
回复 2# michaelll
我知道有区别,但是,我不知道有什么区别。
发表于 2012-9-27 03:26:26 | 显示全部楼层
clock source latency 传播不一样
 楼主| 发表于 2012-9-27 09:26:54 | 显示全部楼层
回复 4# yin_wt

您好,还有其他方面的区别吗?谢谢。
发表于 2012-9-27 21:42:11 | 显示全部楼层
本帖最后由 joemool 于 2012-9-27 21:45 编辑

《Static Timing Analysis for Nanometer Designs A Practical Approach》
J. Bhasker • Rakesh Chadha

Page 190 ~ 191

Can a new clock, that is, a master clock, be defined at the output of the flipflop instead of a generated clock? The answer is yes, that it is indeed possible. However, there are some disadvantages. Defining a master clock instead of a generated clock creates a new clock domain. This is not a problem in general except that there are more clock domains to deal with in setting up the constraints for STA. Defining the new clock as a generated clock does not create a new clock domain, and the generated clock is considered to be in phase with its master clock. The generated clock does not require additional constraints to be developed. Thus, one must attempt to define a new internally generated clock as a generated clock instead of deciding to declare it as another master clock.

Another important difference between a master clock and a generated clock is the notion of clock origin. In a master clock, the origin of the clock is at the point of definition of the master clock. In a generated clock, the clock origin is that of the master clock and not that of the generated clock. This implies that in a clock path report, the start point of a clock path is always the master clock definition point. This is a big advantage of a generated clock over defining a new master clock as the source latency is not automatically included for the case of a new master clock.

评论:
两种方式来定义gen_clk都是可行的,但是采用create_clock并不是最佳方案。1,因为无法继承master clock的属性,不利于分析时钟结构;2,在STA过程中,无法看到gen_clk的原始来源,不利于debug timing。
因此,建议,甚至强制要求所有应该用generated_clock进行定义的地方都这么定义。

详情请去仔细看书!

Thanks & Regards,

Joemool
 楼主| 发表于 2012-9-28 09:30:41 | 显示全部楼层
回复 6# joemool
您好,昨天在ICC是试过了,generated clock可以继承master clock的latency,但是,不能继承uncertainty和transition信息。
发表于 2012-9-28 09:39:01 | 显示全部楼层




   具体的情况,自己去做实验吧。
发表于 2014-7-10 13:52:50 | 显示全部楼层
回复 6# joemool
找这本书来好好研究一下。
发表于 2014-7-10 15:03:14 | 显示全部楼层
回复 8# joemool


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