AES設計經典 - AES on FPGA from the fastest to the smallest

zylin614 · 发表于 2012-9-22 09:57:36

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AES on FPGA from the fastest to the smallest

Abstract:
Two new FPGA designs for the Advanced Encryption Standard (AES) are presented. The first is believed to the fastest, achieving 25Gbps throughput using a Xilinx Spartan-III (XC3S2000) device. The second is believed to be the smallest and fits into a Xilinx Spartan-II (XC2S15) device, only requiring two block memories and 124 slices to achieve a throughput of 2.2 Mbps.

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