本帖最后由 scuay 于 2012-8-31 11:44 编辑
本压缩包系列整理了1137篇各种论文，文件名都已经用论文标题命名。
由于个人精力有限，整理的不是很规范，个别文件可能不是论文，还望大家多多包涵。
以后搜集到新论文，还会再次打包上传，以便大家补充更新。
本次总共106个压缩包，1.54GB。
论文目录（部分）：
(phd)$超高频射频电子标签芯片中低功耗电路研究.nh
(phd)(13MHz)射频识别标签芯片关键技术的研究与实现.kdh
(phd)RFID与无线网络融合关键理论和技术研究（北京邮电）.nh
(phd)RFID关键技术研究与实现（中国科学技术大学）.nh
(phd)UHF频段射频识别系统与天线研究（华南理工）.nh
(phd)低功耗低成本无源射频识别标签芯片的研究与设计.nh
(phd)低功耗芯片技术的研究及其RFID中的应用.nh
(phd)基于片上天线的无源超高频射频识别标签的射频前端设计.nh
(phd)基于神经网络的RFID标签天线印刷品质的优化研究（南京林业）.kdh
(phd)无源超高频电子标签芯片设计研究(hs).kdh
(phd)超高频射频识别_RFID_中的若干问题研究.nh
0.9-V Rail-to-Rail Operational Amplifiers with Adaptive Threshold Voltage Control.pdf
05575247.pdf
0_8_mSOI_CMOSSPICE器件模型参数提取.kdh
1.0 GBPS LVDS TRANSCEIVER DESIGN FOR LCD PANELSs.PDF
1.5GHz fully differential latched current comparator with 20nA of sensitivity.pdf
1.5GSPS 4-bit flash ADC using 0.18?m CMOS.pdf
1.8-V 800-Mbspin DDR2 and 2.5-V 400-Mbspin.pdf
1.A 5-Gb per s ADC-Based Feed-Forward CDR in 65 nm CMOS.pdf
1.A Compact Wideband CMOS Low Noise Amplifier With Gain Flatness Enhancement.pdf
1.A Low-Power Low-Cost Fully-Integrated 60-GHz Transceiver System With OOK Modulation and On-Board Antenna Assembly.pdf
1.Introduction to the Special Issue on the 2009 IEEE International Solid-State Circuits Conference.pdf
1.Introduction to the Special Issue on the 2009 IEEE Radio Frequency Integrated Circuits (RFIC) Symposium.pdf
1.Introduction to the Special Issue on the 2009 Symposium on VLSI Circuits.pdf
1.Introduction to the Special Issue on the 35th European Solid-State Circuits Conference (ESSCIRC 2009).pdf
1.Introduction to the Special Issue on the IEEE 2009 Custom Integrated Circuits Conference.pdf
1.Introduction to the Special Section on the 2009 Asian Solid-State Circuits Conference (A-SSCC'09).pdf
1.Introduction to the Special Section on the 23rd Bipolar-BiCMOS Circuits and Technology Meeting.pdf
10 Bits 100MSs Digital to Analog Converter for IEEE 802.11a.pdf
10.A 0.02-mm 9-Bit 50-MS per s Cyclic ADC in 90-nm Digital CMOS Technology.pdf
10.A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.pdf
10.A 2.4-GHz Low-Power All-Digital Phase-Locked Loop.pdf
10.A 300 mV 494GOPS per W Reconfigurable Dual-Supply 4-Way SIMD Vector Processing Accelerator in 45 nm CMOS.pdf
10.A 40 Gs per s Time Interleaved ADC Using SiGe BiCMOS Technology.pdf
10.A Phase-Selecting Digital Phase-Locked Loop With Bandwidth Tracking in 65-nm CMOS Technology.pdf
10.An Amorphous-Silicon Operational Amplifier and Its Application to a 4-Bit Digital-to-Analog Converter.pdf
10.Discrete-Time Mixing Receiver Architecture for RF-Sampling Software-Defined Radio.pdf
10.Multirate Cascaded Discrete-Time Low-Pass ΔΣ Modulator for GSM-Bluetooth-UMTS.pdf
10.Power Reduction in Continuous-Time Delta-Sigma Modulators Using the Assisted Opamp Technique.pdf
11.187 MHz Subthreshold-Supply Charge-Recovery FIR.pdf
11.A 12 bit 50 MS per s CMOS Nyquist AD Converter With a Fully Differential Class-AB Switched Op-Amp.pdf
11.A 3 3.8 Gb per s Four-Wire High Speed I-O Link Based on CDMA-Like Crosstalk Cancellation.pdf
11.A 3-V, 6-Bit C-2C Digital-to-Analog Converter Using Complementary Organic Thin-Film Transistors on Glass.pdf
11.A 4.0 GHz 291 Mb Voltage-Scalable SRAM Design in a 32 nm High-k + Metal-Gate CMOS Technology With Integrated Power Management.pdf
11.A Duty-Cycle-Distortion-Tolerant Half-Delay-Line Low-Power Fast-Lock-in All-Digital Delay-Locked Loop.pdf
11.A Low-Power Wide-Range Clock Synchronizer With Predictive-Delay-Adjustment Scheme for Continuous Voltage Scaling in DVFS.pdf
11.A Low-Voltage Energy-Sampling IR-UWB Digital Baseband Employing Quadratic Correlation.pdf
11.An 11.1 mW 42 MS per s 10 b ADC With Two-Step Settling in 0.18 m CMOS.pdf
11.Far-Field On-Chip Antennas Monolithically Integrated in a Wireless-Powered 5.8-GHz Downlink-UWB Uplink RFID Tag in 0.18- Standard CMOS.pdf
12-bit low-power fully differential switched capacitor noncalibrating successive approximation ADC with 1 MSs.pdf
12-Bits 50 MHz Pipelined Low-Voltage ADC Design.pdf
12.8 Gb 3-D DDR3 DRAM Using Through-Silicon-Via Technology.pdf
12.A 1.27 GHz, All-Digital Spread Spectrum Clock Generator or Synthesizer in 65 nm CMOS.pdf
12.A 5 Gbps 0.13 m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links.pdf
12.A Micro-Power EEG Acquisition SoC With Integrated Feature Extraction Processor for a Chronic Seizure Detection System.pdf
12.An 80 mW 40 Gb per s 7-Tap 0.5T-Spaced Feed-Forward Equalizer in 65 nm CMOS.pdf
12.An Ultralow-Power Receiver for Wireless Sensor Networks.pdf
12.Closed-Loop Class-D Amplifier With Nonlinear Loop Integrators.pdf
12.Energy-Efficient Design Methodologies：High-Performance VLSI Adders.pdf
12.Exploring Asynchronous Design Techniques for Process-Tolerant and Energy-Efficient Subthreshold Operation.pdf
12.Tera-Scale Performance Machine Learning SoC (MLSoC) With Dual Stream Processor Architecture for Multimedia Content Analysis.pdf
12位50MHz流水线ADC采样保持电路实现.pdf
12位逐次逼近型A_D转换器的设计.kdh
13.A 118.4 GB per s Multi-Casting Network-on-Chip With Hierarchical Star-Ring Combined Topology for Real-Time Object Recognition.pdf
13.A 26.9 K 314.5 Mbps Soft (32400,32208) BCH Decoder Chip for DVB-S2 System.pdf
13.A 74.8 mW Soft-Output Detector IC for 8 8 Spatial-Multiplexing MIMO Communications.pdf
13.A 75 nm 7 Gb per s per pin 1 Gb GDDR5 Graphics Memory Device With Bandwidth Improvement Techniques.pdf
13.A Differential Data-Aware Power-Supplied (D AP) 8T SRAM Cell With Expanded Write-Read Stabilities for Lower VDDmin Applications.pdf
13.A Low THD, Low Power, High Output-Swing Time-Mode-Based Tunable Oscillator Via Digital Harmonic-Cancellation Technique.pdf
13.All-Digital Circuits for Measurement of Spatial Variation in Digital Circuits.pdf
13.An All-In-One Silicon Odometer for Separately Monitoring HCI, BTI, and TDDB.pdf
13.Cognitive Radio Design Challenges and Techniques.pdf
13.Current-Mode, WCDMA Channel Filter With In-Band Noise Shaping.pdf
14.2 Gb per s 15 pJ per b per chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking.pdf
14.A 116 fps-74 mW Heterogeneous 3D-Media Processor for 3-D Display Applications.pdf
14.A 12-Bit Vernier Ring Time-to-Digital Converter in 0.13 $mu{hbox {m}}$ CMOS Technology.pdf
14.A 2.5-GHz, 6.9-mW, 45-nm-LP CMOS, ΔΣ Modulator Based on Standard Cell Design With Time-Interleaving.pdf
14.A Floating-Gate-Based Field-Programmable Analog Array.pdf
14.A Low-Supply-Voltage-Operation SRAM With HCI Trimmed Sense Amplifiers.pdf
14.A Sub- W Embedded CMOS Temperature Sensor for RFID Food Monitoring Application.pdf
14.Multi-Level Amplitude Modulation of a 16.8-GHz Class-E Power Amplifier With Negative Resistance Enhanced Power Gain for 400-Mbps Data Transmission.pdf
14.Progress and Challenges Towards Terahertz CMOS Integrated Circuits.pdf
14.Turbo Decoder Using Contention-Free Interleaver and Parallel Architecture.pdf
15.0.5-V Low-$V _{rm T}$ CMOS Preamplifier for Low-Power and High-Speed Gigabit-DRAM Arrays.pdf
15.A 1.6 GB per s DDR2 128 Mb Chain FeRAM With Scalable Octal Bitline and Sensing Schemes.pdf
15.A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator With 67.7 dB SNDR Using Time-Domain Quantization and Feedback.pdf
15.A Merged CMOS Digital Near-End Crosstalk Canceller and Analog Equalizer for Multi-Lane Serial-Link Receivers.pdf
15.An Efficient 10GBASE-T Ethernet LDPC Decoder Design With Low Error Floors.pdf
15.An Ultra-Low-Energy Multi-Standard JPEG Co-Processor in 65 nm CMOS With Sub-Near Threshold Supply Voltage.pdf
15.Capacitive-Sensing Circuit Technique for Image Quality Improvement on Fingerprint Sensor LSIs.pdf
15.Correction to “A 1 MHz Bandwidth, 6 GHz 0.18 m CMOS Type-I Fractional-N Synthesizer for WiMAX Applications” [Dec 09 3244-3252].pdf
15.Injection-Locked CMOS Frequency Doublers for -Wave and mm-Wave Applications.pdf
16.3-D System Integration of Processor and Multi-Stacked SRAMs Using Inductive-Coupling Link.pdf
16.A 0.5-$mu$ V$_{rm rms}$ 12-$mu$ W Wirelessly Powered Patch-Type Healthcare Sensor for Wearable Body Sensor Network.pdf
16.A Pulsed UWB Receiver SoC for Insect Motion Control.pdf
16.Patent Abstracts.pdf
16.Power Efficient Gigabit Communication Over Capacitively Driven RC-Limited On-Chip Interconnects.pdf
16.Spur Reduction Techniques for Phase-Locked Loops Exploiting A Sub-Sampling Phase Detector.pdf
16.Triple-Push Operation for Combined Oscillation or Divison Functionality in Millimeter-Wave Frequency Synthesizers.pdf
17.A 4 kb Metal-Fuse OTP-ROM Macro Featuring a 2 V Programmable 1.37 $mu$ m$^{2}$ 1T1R Bit Cell in 32 nm High-k Metal-Gate CMOS.pdf
17.A Bulk Acoustic Wave (BAW) Based Transceiver for an In-Tire-Pressure Monitoring Sensor Node.pdf
17.A Low-Energy Inductive Coupling Transceiver With Cm-Range 50-Mbps Data Communication in Mobile Device Applications.pdf
17.A Low-Phase-Noise Multi-Phase Oscillator Based on Left-Handed LC-Ring.pdf
17.An Active Transmitter Leakage Suppression Technique for CMOS SAW-Less CDMA Receivers.pdf
17.An Output-Capacitorless Low-Dropout Regulator With Direct Voltage-Spike Detection.pdf
18.A 0.5 mm$^{2}$ Power-Scalable 0.5–3.8-GHz CMOS DT-SDR Receiver With Second-Order RF Band-Pass Sampler.pdf
18.A 32-Mb SPRAM With 2T1R Memory Cell, Localized Bi-Directional Write Driver and `1' or `0' Dual-Array Equalized Reference Scheme.pdf
18.A 5.2 mW Self-Configured Wearable Body Sensor Network Controller and a 12 W Wirelessly Powered Sensor for a Continuous Health Monitoring System.pdf
18.Digitally Equalized CMOS Transmitter Front-End With Integrated Power Amplifier.pdf
18.Distributed Parametric Resonator：A Passive CMOS Frequency Divider.pdf
18.Switch-Matrix-Based High-Density Microelectrode Array in CMOS Technology.pdf
19.A 0.7- m BiCMOS Electrostatic Energy-Harvesting System IC.pdf
19.A 1.3-GHz 350-mW Hybrid Direct Digital Frequency Synthesizer in 90-nm CMOS.pdf
19.A 31 ns Random Cycle VCAT-Based 4F $^{2}$ DRAM With Manufacturability and Enhanced Cell Efficiency.pdf
19.A Heterogeneous Digital Signal Processor for Dynamically Reconfigurable Computing.pdf
19.A Low SIR Impulse-UWB Transceiver Utilizing Chirp FSK in 0.18 $mu{rm m}$ CMOS.pdf
19.An Efficient Piezoelectric Energy Harvesting Interface Circuit Using a Bias-Flip Rectifier and Shared Inductor.pdf
1V 10-bit successive approximation ADC for low power biomedical applications.pdf
2.24-Bit 5.0 GHz Direct Digital Synthesizer RFIC With Direct Digital Modulations in 0.13 $mu$ m SiGe BiCMOS Technology.pdf
2.A 120 dB Dynamic Range 400 mW Class-D Speaker Driver With Fourth-Order PWM Modulator.pdf
2.A 45 nm 8-Core Enterprise Xeon Processor.pdf
2.A CMOS 6-mW 10-bit 100-MSps Two-Step ADC.pdf
2.A Current Reuse Quadrature GPS Receiver in 0.13um CMOS.pdf
2.A Fifth-Order Continuous-Time Delta-Sigma Modulator With Single-Opamp Resonator.pdf
2.A High-Resolution Low-Power Incremental ADC With Extended Range for Biosensor Arrays.pdf
2.A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications.pdf
2.Energy Supply and ULP Detection Circuits for an RFID Localization System in 130 nm CMOS.pdf
2.Software Assisted Digital RF Processor (DRP?) for Single-Chip GSM Radio in 90 nm CMOS.pdf
20.A 4.3 GB pre s Mobile Memory Interface With Power-Efficient Bandwidth Scaling.pdf
20.A High-Speed Low-Power Multi-VDD CMOS-SIMOX SRAM With LV-TTL Level Input-Output Pins—Write-Read Assist Techniques for 1-V Operated Memory Cells.pdf
20.A mm-Wave Power-Harvesting RFID Tag in 90 nm CMOS.pdf
20.A System-on-Chip EPC Gen-2 Passive UHF RFID Tag With Embedded Temperature Sensor.pdf
20.An Integrated Power Supply System for Low Power 3.3 V Electronics Using On-Chip Polymer Electrolyte Membrane (PEM) Fuel Cells.pdf
20.Correction on “A 5-Gb per s per pin Transceiver for DDR Memory Interface With a Crosstalk Suppression Scheme” [Aug 09 2222-2232].pdf
2008_JSSC_Bruce Wooley_A 77-dB Dynamic Range, 7.5-MHz Hybrid Continuous-Time_Discrete-Time Cascaded sigma delta Modulator.pdf
2008_JSSC_Gabor C.Temes_A 0.9 V 92 dB Double-Sampled Switched-RC Delta-Sigma Audio ADC.pdf
2008_JSSC_Jacob Abraham_A Single-Die 124 dB Stereo Audio Delta-Sigma.pdf
2009_JSSC_Franco Maloberti_A 107.4 dB SNR Multi-Bit Sigma Delta ADC With.pdf
2009_JSSC_Gabor C.Temes_An 8.1 mW, 82 dB Delta-Sigma ADC With.pdf
2009_JSSC_Yoshihisa Fujimoto_A 100 MS_s 4 MHz Bandwidth 70 dB SNR sigma delta ADC in 90 nm CMOS.pdf
2010_JSSC_Bruce Wooley_A High-Resolution Low-Power Incremental sigma delta ADC With Extended Range for Biosensor Arrays.pdf
2010_JSSC_Ian Galton_A Mostly-Digital Variable-Rate Continuous-Time Delta-Sigma Modulator ADC.pdf
20mW, 125 Msps, 10 bit Pipelined ADC in 65nm Standard Digital CMOS Process.pdf
21.1 An 18b 12.5MHz ADC with 93dB SNR.pdf
21.2 A 12b 22.5 45MS s 3.0mW 0.059mm2 CMOS SAR ADC achieving over 90dB SFDR.pdf
21.3 A 0.06mm2 8.9b ENOB 40MS s pipelined SAR ADC in 65nm CMOS.pdf
21.4 A 10b 50MS s 820uW SAR ADC with on-chip digital calibration.pdf
21.5 A 10b 100MS s 1.13mW SAR ADC with Binary-Scaled Error Compensation.pdf
21.6 A 30fJ conversion-step 8b 0-to-10MS s asynchronous SAR ADC in 90nm CMOS.pdf
21.7 A 40GS s 6b ADC in 65nm CMOS.pdf
21.A 0.6 mW per Gb per s, 6.4–7.2 Gb per s Serial Link Receiver Using Local Injection-Locked Ring Oscillators in 90 nm CMOS.pdf
21.A 2$,times,$ 25-Gbps Receiver With 2：5 DMUX for 100-Gbps Ethernet.pdf
21.A 9-bit, 14 μW and 0.06 mm $^{2}$ Pulse Position Modulation ADC in 90 nm Digital CMOS.pdf
21.A GHz Spintronic-Based RF Oscillator.pdf
21.Correction to “An 8.1 mW, 82 dB Delta-Sigma ADC With 1.9 MHz BW and 98 dB THD” [Aug 09 2202-2211].pdf
21.Correction to “Baseband and Audio Mixed-Signal Front-End IC for GSM or EDGE Applications” [Jun 06 1364-1379].pdf
22.A 21-Gb per s 87-mW Transceiver With FFE or DFE or Analog Equalizer in 65-nm CMOS Technology.pdf
22.A High-Speed Current-Mode Data Driver With Push-Pull Transient Current Feedforward for Full-HD AMOLED Displays.pdf
22.Phase Error Calibration Technique for Rotary Traveling Wave Oscillators.pdf
22.Silicon Resonator Based 3.2 W Real Time Clock With 10 ppm Frequency Accuracy.pdf
23.50–250 MHz ΔΣ DLL for Clock Synchronization.pdf
23.A 0.2 mm$^{2}$ , 27 Mbps 3 mW ADC or FFT-Less FDM BAN Receiver With Energy Exploitation Capability.pdf
23.A 6- W Chip-Area-Efficient Output-Capacitorless LDO in 90-nm CMOS Technology.pdf
23.Optical I-O Technology for Tera-Scale Computing.pdf
24.A 77 GHz 90 nm CMOS Transceiver for FMCW Radar Applications.pdf
24.An Efficiency-Enhanced Auto-Reconfigurable 2 or 3 SC Charge Pump for Transcutaneous Power Transmission.pdf
24.Stretchable EMI Measurement Sheet With 8 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 m Silicon CMOS LSIs for Electric and Magnetic Field Detection.pdf
24.The Speed–Power Trade-Off in the Design of CMOS True-Single-Phase-Clock Dividers.pdf
25.A Low-Power Fast-Transient 90-nm Low-Dropout Regulator With Multiple Small-Gain Stages.pdf
25.An Integrated ISFETs Instrumentation System in Standard CMOS Technology.pdf
26.A 64 Channel Programmable Closed-Loop Neurostimulator With 8 Channel Neural Amplifier and Logarithmic ADC.pdf
26.Capacitor-Less Design of Power-Rail ESD Clamp Circuit With Adjustable Holding Voltage for On-Chip ESD Protection.pdf
27.An Integrated 256-Channel Epiretinal Prosthesis.pdf
2_45GHz高线性功率放大器设计.pdf
3.3伏，100M采样频率，10比特流水线结构摸数转换器的设计和低功耗实现.pdf
3.5–10 Gb per s 70 mW Burst Mode AC Coupled Receiver in 90-nm CMOS.pdf
3.A 10-bit 100-MSps Reference-Free SAR ADC in 90 nm CMOS.pdf
3.A 60 GHz Power Amplifier With 14.5 dBm Saturation Power and 25% Peak PAE in CMOS 65 nm SOI.pdf
3.A Background Self-Calibrated 6b 2.7 GS per s ADC With Cascade-Calibrated Folding-Interpolating Architecture.pdf
3.A Chip-Stacked Memory for On-Chip SRAM-Rich SoCs and Processors.pdf
3.A DVS Embedded Power Management for High Efficiency Integrated SoC in UWB System.pdf
3.A Millimeter-Wave (23–32 GHz) Wideband BiCMOS Low-Noise Amplifier.pdf
3.An Integrated 0.6–4.6 GHz, 5–7 GHz, 10–14 GHz, and 20–28 GHz Frequency Synthesizer for Software-Defined Radio Applications.pdf
3.Auto Correction Feedback for Ripple Suppression in a Chopper Amplifier.pdf
3.Linearized Dual-Band Power Amplifiers With Integrated Baluns in 65 nm CMOS for a 2 2 802.11n MIMO WLAN SoC.pdf
3rd order curvature corrected Bandgrip Cell.pdf
4.A 0.06 mm$^{2}$ 11 mW Local Oscillator for the GSM Standard in 65 nm CMOS.pdf
4.A 0.6-V Zero-IF or Low-IF Receiver With Integrated Fractional-N Synthesizer for 2.4-GHz ISM-Band Applications.pdf
4.A 300–800 MHz Tunable Filter and Linearized LNA Applied in a Low-Noise Harmonic-Rejection RF-Sampling Receiver.pdf
4.A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth.pdf
4.An 11-Bit 8.6 GHz Direct Digital Synthesizer MMIC With 10-Bit Segmented Sine-Weighted DAC.pdf
4.An Integrated Linear Regulator With Fast Output Voltage Transition for Dual-Supply SRAMs in DVFS Systems.pdf
4.An X-Band Transformer-Coupled Varactor-Less Quadrature Current-Controlled Oscillator in 0.18 SiGe BiCMOS Technology.pdf
4.Area- and Power-Efficient Monolithic Buck Converters With Pseudo-Type III Compensation.pdf
4.Design of a 79 dB 80 MHz 8X-OSR Hybrid Delta-Sigma or Pipelined ADC.pdf
4.Securing Encryption Systems With a Switched Capacitor Current Equalizer.pdf
40-Gbs High-Gain Distributed Amplifiers With Cascaded Gain Stages in 0.18-μm CMOS.pdf
5.A 0.13 SiGe BiCMOS Technology Featuring fT-fmax of 240-330 GHz and Gate Delays Below 3 ps.pdf
5.A 10-bit 50-MS per s SAR ADC With a Monotonic Capacitor Switching Procedure.pdf
5.A 200 μA Duty-Cycled PLL for Wireless Sensor Nodes in 65 nm CMOS.pdf
5.A 201.4 GOPS 496 mW Real-Time Multi-Object Recognition Processor With Bio-Inspired Neural Perception Engine.pdf
5.A 58–65 GHz Neutralized CMOS Power Amplifier With PAE Above 10% at 1-V Supply.pdf
5.A Dynamic Phase Error Compensation Technique for Fast-Locking Phase-Locked Loops.pdf
5.A PVT Tolerant 10 to 500 MHz All-Digital Phase-Locked Loop With Coupled TDC and DCO.pdf
5.An IF Bandpass Filter Based on a Low Distortion Transconductor.pdf
5.Continuous-Time Input Pipeline ADCs.pdf
5.The Experimental Demonstration of a SASP-Based Full Software Radio Receiver.pdf
500MSs 4-b Time Interleaved SAR ADC using Novel DAC Architecture.pdf
56M~806M宽频带Double-Vonversion混频器设计.pdf
6 bit Current-Steering DAC for the Pipeline ADC.pdf
6.A 1 GS per s 6 Bit 6.7 mW Successive Approximation ADC Using Asynchronous Processing.pdf
6.A 20 mV Input Boost Converter With Efficient Digital Control for Thermoelectric Energy Harvesting.pdf
6.A 212 MPixels per s 4096 2160p Multiview Video Encoder Chip for 3D or Quad Full HDTV Applications.pdf
6.A Four-Channel Beamforming Down-Converter in 90-nm CMOS Utilizing Phase-Oversampling.pdf
6.A Single-Chip CMOS UHF RFID Reader Transceiver for Chinese Mobile Applications.pdf
6.An Active Feedback Interference Cancellation Technique for Blocker Filtering in RF Receiver Front-Ends.pdf
6.An On-Chip CMOS Relaxation Oscillator With Voltage Averaging Feedback.pdf
6.Dynamic Quadrant Swapping Scheme Implemented in a Post Conversion Block for I, Q Mismatch Reduction in a DQPSK Receiver.pdf
6.High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique.pdf
6.Parametric Mismatch Characterization for Mixed-Signal Technologies.pdf
7.A 25-GHz Compact Low-Power Phased-Array Receiver With Continuous Beam Steering in CMOS Technology.pdf
7.A 250 MHz 14 dB-NF 73 dB-Gain 82 dB-DR Analog Baseband Chain With Digital-Assisted DC-Offset Calibration for Ultra-Wideband.pdf
7.A 3.1 mW Continuous-Time ΔΣ Modulator With 5-Bit Successive Approximation Quantizer for WCDMA.pdf
7.A 342 mW Mobile Application Processor With Full-HD Multi-Standard Video Codec and Tile-Based Address-Translation Circuits.pdf
7.A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems.pdf
7.A 7.1 mW, 10 GHz All Digital Frequency Synthesizer With Dynamically Reconfigured Digital Loop Filter in 90 nm CMOS Technology.pdf
7.A Single-Bit 500 kHz-10 MHz Multimode Power-Performance Scalable 83-to-67 dB DR CTΔΣ for SDR in 90 nm Digital CMOS.pdf
7.An 11.1 Gbps Analog PRML Receiver for Electronic Dispersion Compensation of Fiber Optic Communications.pdf
7.Effect of Substrate Contact Shape and Placement on RF Characteristics of 45 nm Low Power CMOS Devices.pdf
7.Multi-Phase 1 GHz Voltage Doubler Charge Pump in 32 nm Logic Process.pdf
8.A 0.5 V Sub-Microwatt CMOS Image Sensor With Pulse-Width Modulation Read-Out.pdf
8.A 10-bit Charge-Redistribution ADC Consuming 1.9 $mu$W at 1 MS per s.pdf
8.A 16$, times $16 Pixel Distance Sensor With In-Pixel Circuitry That Tolerates 150 klx of Ambient Light.pdf
8.A 500 mW ADC-Based CMOS AFE With Digital Calibration for 10 Gb per s Serial Links Over KR-Backplane and Multimode Fiber.pdf
8.A Low-Power Continuously-Calibrated Clock Recovery Circuit for UHF RFID EPC Class-1 Generation-2 Transponders.pdf
8.A Quantization Error Minimization Method Using DDS-DAC for Wideband Fractional-N Frequency Synthesizer.pdf
8.A Reconfigurable, 130 nm CMOS 108 pJ per pulse, Fully Integrated IR-UWB Receiver for Communication and Precise Ranging.pdf
8.An Embedded All-Digital Circuit to Measure PLL Response.pdf
8.Attenuation-Predistortion Linearization of CMOS OTAs With Digital Correction of Process Variations in OTA-C Filter Applications.pdf
8.Low-Power Quadrature Receivers for ZigBee (IEEE 802.15.4) Applications.pdf
8位逐次逼近A_D转换器的优化设计.nh
9.A 1 GHz Digital Channel Multiplexer for Satellite Outdoor Unit.pdf
9.A 134-Pixel CMOS Sensor for Combined Time-of-Flight and Optical Triangulation 3-D Imaging.pdf
9.A 60-GHz OOK Receiver With an On-Chip Antenna in 90 nm CMOS.pdf
9.A 700-$mu$ W Wireless Sensor Node SoC for Continuous Real-Time Health Monitoring.pdf
9.A Fractional-N PLL for Multiband (0.8–6 GHz) Communications Using Binary-Weighted DA Differentiator and Offset-Frequency Δ-Σ Modulator.pdf
9.A Low-Power Capacitive Charge Pump Based Pipelined ADC.pdf
9.A Time-Domain SAR Smart Temperature Sensor With Curvature Compensation and a 3σ Inaccuracy of ?0.4°C ～ +0.6°C Over a 0°C to 90°C Range.pdf
9.An Energy-Efficient Equalized Transceiver for RC-Dominant Channels.pdf
9.LMS-Based Noise Leakage Calibration of Cascaded Continuous-Time Modulators.pdf
9.Two-Dimensions Vernier Time-to-Digital Converter.pdf
A 0.05-mm2 110-μW 10-b self-calibrating successive approximation ADC core in 0.18 CMOS.pdf
A 0.3mm2 90-to-770MHz Fractional-N Synthesizer for a Digital TV Tuner.pdf
A 0.3–1.4 GHz All-Digital Fractional-N PLL With Adaptive Loop Gain Controller.pdf
A 0.5-V 1-Msps Track-and-Hold Circuit.pdf
A 0.5V 8bit 10Msps Pipelined ADC in 90nm CMOS.pdf
A 0.8V 10b 8OMSs 6.5mW Pipelined ADC with Regulated Overdrive Voltage Biasing.pdf
A 0.9-V 10-bit 100-MSamples pipelined ADC using switched-RC and opamp sharing techniques.pdf
A 0.9V 10-bit 100 MSs switched-RC pipelined ADC without using a front-end SH in 90nm CMOS.pdf
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 $mu$ m CMOS.pdf
A 1 GHz ADPLL With a 1.25 ps Minimum-Resolution Sub-Exponent TDC in 0.18 um CMOS.pdf
A 1-Gbspin 512-Mb DDRII SDRAM Using.pdf
A 1-GSs CMOS 6-bit flash ADC with an offset calibrating method.pdf
A 1-V 100-MSs 8-bit CMOS Switched-Opamp.pdf
A 1.2 V Bandgap Reference Based on Transimpedance Amplifier.pdf
A 1.2-V 10-$mu$ W NPN-Based Temperature Sensor in 65-nm CMOS With an Inaccuracy of 0.2 $^{circ}$ C (3$sigma$ ) From $-$ 70 $^{circ}$ C to 125 $^{circ}$ C.pdf
A 1.2-V Piecewise Curvature-Corrected Bandgap Reference in 0.5 m CMOS Process.pdf
A 1.2-V, 12-bit, 200MSample 90nm.pdf
A 1.2V 200-MSs 10-bit folding and interpolating ADC in 0.13-μm CMOS.pdf
A 1.2V 4.5mW 10b 100MSs Pipeline ADC in a 65nm CMOS.pdf
A 1.5MSs 6-bit ADC with 0.5V supply.pdf
A 1.8-mW CMOS Modulator with Integrated Mixer for AD Conversion of IF Signals.pdf
A 1.8-V 700-Mbspin 512-Mb DDR-II SDRAM.pdf
A 1.8-V High-Precision Compensated CMOS Bandgap Reference.pdf
A 1.8-V High-Precision Compensated CMOS.pdf
A 1.8V 10b 210MSs CMOS Pipelined ADC Featuring 86dB SFDR without Calibration.pdf
A 1.8V 36-mW 11-bit 80MSs pipelined ADC using capacitor and opamp sharing.pdf
A 10-bit 1-GSample.pdf
A 10-BIT 100MSs pipelined ADC IN 0.18μm CMOS technology.pdf
A 10-bit 205-MSs 1.0- mm2 90-nm CMOS Pipeline ADC for Flat Panel Display Applications.pdf
A 10-bit 250-MS.pdf
A 10-bit 2GHz Current-Steering CMOS DA Converter.pdf
A 10-Bit 50-MSPS Pipelined CMOS ADC.pdf
A 10-bit 500-MSs 124-mW Subranging Folding ADC in 0.13 CMOS.pdf
A 10-bit 8.3MSs switched-current successive approximation ADC for column-parallel imagers.pdf
A 10-bit, 1.8-GSs Time-Interleaved Pipeline ADC.pdf
A 10-MHz Signal Bandwidth Cartesian Loop Transmitter Capable of Off-Chip PA Linearization.pdf
A 100MSs recycling 2-step ADC embedding programmable gain amplification for DVB satellite.pdf
A 10b 160MSs 84mW 1V Subranging ADC in 90nm CMOS.pdf
A 10b 170MSs CMOS Pipelined ADC Featuring 84dB SFDR without Calibration.pdf
A 10b 200MSs pipelined folding ADC with offset calibration.pdf
A 10b 205MSs 1mm2 90nm CMOS Pipeline ADC for Flat-Panel Display Applications.pdf
A 10MSs 11-b 0.19mm Algorithmic ADC with Improved Clocking.pdf
A 12 bit 200 MHz Low Glitch.pdf
A 12-bit 1MSps Non-calibrating SAR A-D Converter based on 90nm CMOS Process.pdf
A 12-bit 320-MSample.pdf
A 12-Bit 75-MSs Pipelined ADC Using Incomplete Settling.pdf
A 12-bit DAC for Space Applications.pdf
A 12-bit Multi-Channel Non-Calibrating Dual-Mode Successive Approximation ADC for Power Management Bus (PMBus) Devices.pdf
A 12.3-mW 12.5-Gb-s Complete Transceiver in 65-nm CMOS Process.pdf
A 12b 500MSample.pdf
A 12th Order Active-RC Filter With Automatic Frequency Tuning for DVB Tuner Applocations邹亮.PDF
A 14-b 30MSs 0.75mm2 Pipelined ADC with On-Chip Digital Self-Calibration.pdf
A 14-bit 100-MSs digitally calibrated binary-weighted current-steering CMOS DAC without calibration ADC.pdf
A 14-bit 100-MSs Digitally Calibrated Binary-Weighted.pdf
A 14-BIT 130-MHZ CMOS CURRENT-STEERING DAC WITH ADJUSTABLE INL.pdf
A 14-bit 130-MSPS current-steering CMOS DAC with 2 x FIR interpolation filter.pdf
A 14-bit 200-MHz Current-Steering DAC With Switching-Sequence Post-Adjustment Calibration.pdf
A 14-BIT DUAL CURRENT-STEERING DAC.pdf
论文目录文件：
paper(20120831)_list.pdf
(278.8 KB, 下载次数: 84 )
第1~20个压缩包：
paper(20120831).part002.rar
(15 MB, 下载次数: 110 )
paper(20120831).part003.rar
(15 MB, 下载次数: 96 )
paper(20120831).part004.rar
(15 MB, 下载次数: 100 )
paper(20120831).part005.rar
(15 MB, 下载次数: 84 )
paper(20120831).part006.rar
(15 MB, 下载次数: 82 )
paper(20120831).part007.rar
(15 MB, 下载次数: 96 )
paper(20120831).part008.rar
(15 MB, 下载次数: 103 )
paper(20120831).part009.rar
(15 MB, 下载次数: 89 )
paper(20120831).part010.rar
(15 MB, 下载次数: 87 )
paper(20120831).part011.rar
(15 MB, 下载次数: 91 )
paper(20120831).part012.rar
(15 MB, 下载次数: 94 )
paper(20120831).part013.rar
(15 MB, 下载次数: 97 )
paper(20120831).part014.rar
(15 MB, 下载次数: 88 )
paper(20120831).part015.rar
(15 MB, 下载次数: 75 )
paper(20120831).part016.rar
(15 MB, 下载次数: 85 )
paper(20120831).part017.rar
(15 MB, 下载次数: 85 )
paper(20120831).part018.rar
(15 MB, 下载次数: 87 )
paper(20120831).part019.rar
(15 MB, 下载次数: 88 )
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发表于 2012-8-31 10:08:13
