Parsing included file '/root/MyTools/vcs2011/doc/examples/uvm-1.0p1/src/dpi/uvm_dpi.svh'.
Parsing included file '/root/MyTools/vcs2011/doc/examples/uvm-1.0p1/src/dpi/uvm_hdl.svh'.
Error-[SE] Syntax error
Following verilog source has syntax error :
"/root/MyTools/vcs2011/doc/examples/uvm-1.0p1/src/dpi/uvm_hdl.svh", 47:
token is 'parameter'
parameter int UVM_HDL_MAX_WIDTH=`UVM_HDL_MAX_WIDTH;
^