I learn the aysnchrous FIFO verilog. But i have a question about the full/empty flag code problem. i don't understand the condition of the full flag. why? Can you simulate the code? the code is as follows:
always @(wr_addr_gray or rd_addr_gray_wsyn2)
begin
if((wr_addr_gray[ADDR_WIDTH]!=rd_addr_gray_wsyn2[ADDR_WIDTH]) &&
(wr_addr_gray[ADDR_WIDTH-1]!=rd_addr_gray_wsyn2[ADDR_WIDTH-1]) &&
(wr_addr_gray[ADDR_WIDTH-2:0]==rd_addr_gray_wsyn2[ADDR_WIDTH-2:0]))
full = 1'b1;
else
full = 1'b0;
end