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[招聘] 西安华芯半导体有限公司(半月更新)

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发表于 2011-12-7 18:20:23 | 显示全部楼层 |阅读模式

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本帖最后由 fcwr_005 于 2013-4-7 17:32 编辑

近期招聘:近期招聘数字IC设计后端工程师,IC验证工程师,IC测试工程师,战略合作官,有意的朋友邮件联系!

1)数字后端设计工程师asic Backend Design Engineer (BE)

Responsibilities:

1. Responsible for developing digital designs with emphasis on backend, including Floor-plan, power planning, Place, CTS and Route.

2. Work with Front-end designers to optimize timing/area/power of the design implementation and perform static timing analysis.

3. Optimization and Verification of layout for tape-out (including RC extraction, ECO, DRC, LVS).

4. Power IR drop analysis and optimization, area and parasitic layout optimization, chip size optimization.

5. Static Timing analysis (Prime Time) and setup/hold fix.

6. Formal Verification for equivalence checking (Formality).

7. Generation of fill structures according to technology requirements.

Requirements:

1. 2-4 years experience in backend design flow (APR) with proven SOC tape-out experience.

2. Experienced in Synopsys/Cadence automatically physical implementation tools and flows (IC-Compiler/ Astro / SOC-Encounter/ Milky-way/ Star-RCX) is a plus.

3. Experience with one or more scripting languages (Perl, TCL, or Shell) to make reusable automatically flow is a plus.

4. Experience and knowledge about FE design (RTL code, flow) and verification is a plus.

5. Good analytical and debugging skills.

6. Good command of English.



2)设计验证工程师Design and Functional Verification Engineer (DFV)

Responsibilities:

1.
According to the design specification, be responsible for the verification plan and verification objective definition.

2.
Test-bench development(modeling, assertions, checkers, monitors, score-board, regressions, coverage), test-case development (sequence, VRAD) and integration.

3.
Work with Random Verification methodology(VMM, OVM, UVM, eRM)

4.
Work as an independent verification engineers to check the design functionality at SOC module level and chip level.

5.
Work as interface with Front-End  and Back-End engineer to optimize or review the design architecture and implementation.

6.
verilog or Vhdl coding according to design specification or external/internal IP integration.

7.
Support the post simulation with gate-level verilog or VHDL netlist.

Requirements:

1.
Either Bachelor, Master or PhD in Microelectronics, Electronic Engineering, or related field 2+ Years of verification working experience.

2.
Experience with  Verification language (SPECMAN/E-language, System-Verilog, Vera)

3.
Experience with RTL coding and simulators (Modelsim, NC-sim).

4.
Basic knowledge of script language (Perl, TCL, C-language and so on)

5.
Knowledge about 2G/3G/LTE handset baseband Architecture, arm, AHB Architecture is a plus.

6.
Knowledge about Baseband chip peripheral(USB2.0/USB3.0, SSIC, MIPI) is a plus.

7.
Team oriented, love to work in young, international and highly motivated teams.

Good command of English


IC人才网(www.jobic.cn)   
       注册简历:
http://www.jobic.cn/c_Resume/Register.aspx
       电话:0755-26490606

 楼主| 发表于 2011-12-15 08:37:05 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-1-9 18:18:17 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-2-1 08:55:04 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-2-8 17:59:13 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-2-13 08:42:03 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系
 楼主| 发表于 2012-2-20 19:01:48 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-2-23 18:33:00 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-3-8 18:02:33 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
 楼主| 发表于 2012-3-11 19:41:41 | 显示全部楼层
近期招聘:近期招聘IC验证工程师,有意的朋友邮件联系!
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