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发表于 2006-9-19 10:30:52
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显示全部楼层
用verilog来实现
module div3(clr,clk,clkout);
input clr,clk;
output clkout;
reg clkreg1,clkreg2;
parameter n=5;
reg[n:0] counter1,counter2;
assign clkout=clkreg1||clkreg2;
always @(posedge clk)
if(clr==1) begin clkreg1=0;counter1=0;end
else begin if(counter1==n-1) begin counter1=0;clkreg1=~clkreg1;end
else if(counter1==(n-1)/2) begin counter1=counter1+1;clkreg1=~clkreg1;end
else begin counter1=counter1+1;end
end
always @(negedge clk)
if(clr==1) begin clkreg2=0;counter2=0;end
else begin if(counter2==n-1) begin counter2=0;clkreg2=~clkreg2;end
else if(counter2==(n-1)/2) begin counter2=counter2+1;clkreg2=~clkreg2;end
else begin counter2=counter2+1;end
end
endmodule |
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