上海数字后端职位信息

KT胡运旺

有兴趣的朋友简历请至digital1@kthr.com
Senior physical design engineer

DESCRIPTION OF FUNCTION & RESPONSIBILITY:

1. Implement APR from netlist to gds to close timing and routing

2. Build high efficient PG mesh to meet IR-drop and EM requirements

3. Fix SI effect

4. Perform ECO and metal spin

5. Support die size estimation

6. Develop utilities/scripts to improve design flow

QUALIFICATION (DETAIL):

Education:

BSEE or MSEE

Experience:

1. Knowledge of any part of the process from netlist handoff to tapeout is a MUST:

Floorplanning

Power planning and signoff

Placement, CTS and routing

SI effect analysis and fixing

Physical verification

2. Hands-on experience on above items is preferred.

3. Scripts development in Perl and TCL

Senior PR engineer

[size=+0]Responsibilities: [size=+0]layout database creation : layout library and Milkyway database creation;
[size=+0]Initial floorplan : Initial chip or subchip level floorplan;
[size=+0]Place & Route: Perform cells placement; Perform global route and detail route; DRC/LVS corrections;
[size=+0]Layout script creation: Create script to perform layout modification;
[size=+0]Create Apollo scheme file to maintain and update Apollo database;
[size=+0]Layout modification: Follow signal integration report to perform necessary modification;
[size=+0]
[size=+0]Requirements:
[size=+0]Bachelor Degree or higher in EE major; more than 5 years P&R working experience;
[size=+0]Knowledge about Solaris/Unix/Linux operating system;
[size=+0]Good command of English in both written and oral format.

APR

APR Job function:
        1. Floor plan, placement, routing , CTS and  timing closure
        2. Power,IR SI verifcaiton
        3. DRC/LVS verification




APR requirement:
1. BS or MS degree in EE or CS related
2. Educational background/experience with logical and physical synthesis, VLSI design, static timing analysis methods and tools, place and route
3. Experienced/interested in one or multiple of Synopsys Astro/ICC, Cadence SOCE
4. Scripting utilizing Perl or Tcl/TK
5. Interested in taking the challenges of 65nm and below physical desig