警告:Warning: PLL "pllo:u_pllo|altpll:altpll_component|pllo_altpll:auto_generated|pll1" input clock inclk[0] is not fully compensated and may have reduced jitter performance because it is fed by a non-dedicated input
但是我的输入引脚明明是专用的clk脚! 在报告里,Inclk0 signal type一栏是Global Clock。
另外不是专用引脚输入到PLL,根本就编译不过,会出错!