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[原创] 【Navabi 2010 新书】Digital System Test and Testable Design: Using HDL Models

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发表于 2010-12-15 22:47:34 | 显示全部楼层 |阅读模式

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Digital System Test and Testable Design
Using hdl Models and Architectures
Navabi
, Zainalabedin
1st Edition., 2011, XVII, 435 p. 100 illus., Hardcover
ISBN: 978-1-4419-7547-8



Due: December 29, 2010


Digital System Test and Testable Design: Using HDL Models and Architectures by: Zainalabedin Navabi This book is about digital system test and testable design. The concepts of testing and testability are treated together with digital design practices and methodologies. The book uses verilog models and testbenches for implementing and explaining fault simulation and test generation algorithms. Extensive use of Verilog and Verilog PLI for test applications is what distinguishes this book from other test and testability books. Verilog eliminates ambiguities in test algorithms and BIST and DFT hardware architectures, and it clearly describes the architecture of the testability hardware and its test sessions. Describing many of the on-chip decompression algorithms in Verilog helps to evaluate these algorithms in terms of hardware overhead and timing, and thus feasibility of using them for System-on-Chip designs. Extensive use of testbenches and testbench development techniques is another unique feature of this book. Using PLI in developing testbenches and virtual testers provides a powerful programming tool, interfaced with hardware described in Verilog. This mixed hardware / software environment facilitates description of complex test programs and test strategies. •Combines design and test •Describes test methods in Verilog and PLI, which makes the methods more understandable and the gates possible to simulate •Simulation of gate models allows fault simulation and test generation, while Verilog testbenches inject faults, evaluate fault coverage and apply new test patterns •Describes DFT, compression, decompression, and BIST techniques in Verilog, which makes the hardware of the architectures easier to understand and allows simulation and evaluation of the testability methods •Virtual testers (Verilog testbenches) play the role of ATEs for driving scan tests and examining the circuit under test •Verilog descriptions of scan designs and BIST architectures are available that can be used in actual designs &#8226LI test utilities developed in-text are available for download •Introductory Video for Verilog basics, software developed in-text, and PLI basics available for download &#8226owerpoint slides available for each chapter

Content Level » Professional/practitioner
Keywords » BIST - BIST Architetures - Design for Test - Digital System Test - Electronic Testing - Fault Modeling - Fault Simulation - HDL - Hardware Description Language - Memory Testing - PLI - Testable Design

Related subjects » Circuits & Systems - Mathematics - Philosophy

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发表于 2010-12-15 23:00:47 | 显示全部楼层
thanks
发表于 2010-12-16 02:43:50 | 显示全部楼层
Thanks.
发表于 2010-12-16 08:03:03 | 显示全部楼层
谢谢分享。
头像被屏蔽
发表于 2010-12-16 08:39:51 | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽
发表于 2010-12-16 08:48:17 | 显示全部楼层
呵呵,谢谢楼主
发表于 2010-12-16 08:50:09 | 显示全部楼层
IC设计方面的书这两年越来越富足了!
发表于 2010-12-16 10:57:43 | 显示全部楼层
谢谢啊
发表于 2010-12-16 11:14:27 | 显示全部楼层
下来看看,谢谢。
发表于 2010-12-16 12:42:18 | 显示全部楼层
Thanks  for shring!Thanks
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