请教高手Astro问题

linglingfa

在刚开始CTS设置clock common options后，出现一些waring
waring：cell port PO2W/PAD with unknow direction,assumed as input direction
waring：cell port PO2W/I with unknow direction,assumed as input direction
waring：cell port PIW/PAD with unknow direction,assumed as input direction
waring：cell port PIW/C with unknow direction,assumed as input direction
waring: i0: PAD is an implicit ignore pin since it is an non-clock pin
waring: i1: PAD is an implicit ignore pin since it is an non-clock pin
我用的SMIC18工艺，其中PO2W PIW 分别是所用的输出信号PAD、输入信号PAD，
i0,i1是连接两个时钟信号的PAD的实例名

    设置完后，通过clock browse观察时钟树结构，只能看到两个时钟信号连接到i0,i1PAD，但是不连接到摆放在core内部的时序元件的时钟引脚上。


时钟树报告如下
**********************************************************************
*
*   Clock Tree Reports
*
*   Tool    : Astro
*   Version : Z-2007.03-SP10 for SUN.64 -- Jan_06,_2009
*   Design  : pre_cts_copy
*   Date    : Fri Aug 27 20:25:46 2010
*
**********************************************************************



======== Clock tree overview ======================================
1. clock clk480
       0 sink pins
       0 gate/macro pins
       1 ignore pins
       0 gate levels
2. clock clk60
       0 sink pins
       0 gate/macro pins
       1 ignore pins
       0 gate levels

Summary
                  total number of clocks : 2
               total number of sink pins : 0
         total number of gate/macro pins : 0
             total number of ignore pins : 2

             maximum number of sink pins : 0
       maximum number of gate/macro pins : 0
           maximum number of ignore pins : 1
           maximum number of gate levels : 0



======== User defined sync pins ======================================


======== Explicit ignored sink pins ======================================
1. clock clk480
2. clock clk60


======== Implicit ignored sink pins ======================================
  C = clock port without trigger edges
  N = non-clock port
  O = open pin
  I = implicit ignore pin
--------------------------------------
1. clock clk480
  (I) clk480
  (N) i0AD
  (I) i0AD
2. clock clk60
  (I) clk60
  (N) i1AD
  (I) i1:PAD


======== Clock domain overlaps ======================================

bill_ycsu

How about make a fake *.lib to define PAD cell function/timing?

zh123456789

时钟信号连接到的pin无clock属性

linglingfa

要怎么解决呀？谢谢了
3# zh123456789

linglingfa

自己顶

wwei10619

呵呵，学习了。

yyu69

学习了。。。。。。。。。。。。。。

microqian

xiexie!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!