在线咨询
eetop公众号 创芯大讲堂 创芯人才网
切换到宽版

EETOP 创芯网论坛 (原名:电子顶级开发网)

手机号码,快捷登录

手机号码,快捷登录

找回密码

  登录   注册  

快捷导航
搜帖子
查看: 5585|回复: 30

DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN

[复制链接]
发表于 2009-9-21 12:39:39 | 显示全部楼层 |阅读模式

马上注册,结交更多好友,享用更多功能,让你轻松玩转社区。

您需要 登录 才可以下载或查看,没有账号?注册

x
DIGITAL COMPUTER ARITHMETIC DATAPATH DESIGN
JAMES E. STINE

Preface ix
1. MOTIVATION 1
1.1 Why Use verilog hdl? 1
1.2 What this book is not : Main Objective 2
1.3 Datapath Design 3
2. VERILOG AT THE RTL LEVEL 7
2.1 Abstraction 7
2.2 Naming Methodology 10
2.2.1 Gate Instances 11
2.2.2 Nets 12
2.2.3 Registers 12
2.2.4 Connection Rules 13
2.2.5 Vectors 14
2.2.6 Memory 14
2.2.7 Nested Modules 15
2.3 Force Feeding Verilog : the Test Bench 16
2.3.1 Test Benches 18
2.4 Other Odds and Ends within Verilog 19
2.4.1 Concatenation 19
2.4.2 Replication 21
2.4.3 Writing to Standard Output 21
2.4.4 Stopping a Simulation 21
2.5 Timing: For Whom the Bell Tolls 22
2.5.1 Delay-based Timing 22
2.5.2 Event-Based Timing 23
2.6 Synopsys DesignWare Intellectual Property (IP) 24
2.7 Verilog 2001 24
2.8 Summary 26
3. ADDITION 27
3.1 Half Adders 28
3.2 Full Adders 28
3.3 Ripple Carry Adders 30
3.4 Ripple Carry Adder/Subtractor 31
3.4.1 Carry Lookahead Adders 34
3.4.1.1 Block Carry Lookahead Generators 36
3.5 Carry Skip Adders 40
3.5.1 Optimizing the Block Size to Reduce Delay 42
3.6 Carry Select Adders 43
3.6.1 Optimizing the Block Size to Reduce Delay 46
3.7 Prefix Addition 47
3.8 Summary 52
4. MULTIPLICATION 55
4.1 Unsigned Binary Multiplication 56
4.2 Carry-Save Concept 56
4.3 Carry-Save Array Multipliers (CSAM) 60
4.4 Tree Multipliers 61
4.4.1 Wallace Tree Multipliers 61
4.4.2 Dadda Tree Multipliers 65
4.4.3 Reduced Area (RA) Multipliers 68
4.5 Truncated Multiplication 71
4.6 Two’s Complement Multiplication 78
4.7 Signed-Digit Numbers 82
4.8 Booth’s algorithm 86
4.8.1 Bitwise Operators 87
4.9 Radix-4 Modified Booth Multipliers 89
4.9.1 Signed Radix-4 Modified Booth Multiplication 91
4.10 Fractional Multiplication 92
4.11 Summary 93
5. DIVISION USING RECURRENCE 103
5.1 Digit Recurrence 104
5.2 Quotient Digit Selection 105
5.2.1 Containment Condition 106
5.2.2 Continuity Condition 106
5.3 On-the-Fly-Conversion 108
5.4 Radix 2 Division 112
5.5 Radix 4 Division with α = 2 and Non-redundant Residual 115
5.5.1 Redundant Adder 118
5.6 Radix 4 Division with α = 2 and Carry-Save Adder 119
5.7 Radix 16 Division with Two Radix 4 Overlapped Stages 122
5.8 Summary 126
6. ELEMENTARY FUNCTIONS 129
6.1 Generic Table Lookup 131
6.2 Constant Approximations 133
6.3 Piecewise Constant Approximation 134
6.4 Linear Approximations 136
6.4.1 Round to Nearest Even 138
6.5 Bipartite Table Methods 141
6.5.1 SBTM and STAM 142
6.6 Shift and Add: CORDIC 147
6.7 Summary 152
7. DIVISION USING MULTIPLICATIVE-BASED
METHODS 161
7.1 Newton-Raphson Method for Reciprocal Approximation 161
7.2 Multiplicative-Divide Using Convergence 166
7.3 Summary 168
References 171
Index 179

Kluwer-_Digital_Computer_Arithmetic_Datapath_Design_Using_Verilog_HDL.pdf

616.8 KB, 下载次数: 172 , 下载积分: 资产 -2 信元, 下载支出 2 信元

pdf文档

发表于 2009-9-21 22:47:06 | 显示全部楼层
duoxie
发表于 2009-9-22 09:57:08 | 显示全部楼层
Thank you for your sharing
发表于 2009-10-5 13:56:10 | 显示全部楼层
thank you!
发表于 2009-10-9 13:23:39 | 显示全部楼层
Thanks
发表于 2009-10-10 19:58:17 | 显示全部楼层
thanks!
发表于 2009-10-10 23:23:56 | 显示全部楼层
good, thanks.
发表于 2009-10-10 23:31:24 | 显示全部楼层
good, thanks.
发表于 2009-10-12 11:53:25 | 显示全部楼层
goodss
发表于 2009-11-22 14:19:32 | 显示全部楼层
韩国哈哈
您需要登录后才可以回帖 登录 | 注册

本版积分规则

关闭

站长推荐 上一条 /1 下一条

×

小黑屋| 关于我们| 联系我们| 在线咨询| 隐私声明| EETOP 创芯网
( 京ICP备:10050787号 京公网安备:11010502037710 )

GMT+8, 2024-3-29 16:09 , Processed in 0.047031 second(s), 12 queries , Gzip On, Redis On.

eetop公众号 创芯大讲堂 创芯人才网
快速回复 返回顶部 返回列表