lexra 4280 datasheet

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1.1. Introduction
This data sheet describes Lexra’s LX4280 processor, a complete mips R3000-class processor subsystem
developed for ease of integration. (See Figure 1 on page 2.) The major subsystems are: the cpu core, Local
Memory Interfaces (LMI) and LBus Controller (LBC). The technology includes optional interfaces to
customer-defined Coprocessors (CI[1-3]) and optional customer extensions to the MIPS ISA (Custom
Engine). The local instruction memories and data memories may include fixed RAM and/or cache; the sizes
are configurable.
The LX4280 pipeline is a dual-issue, six-stage architecture. Pipe A executes data memory access and all
MIPS instructions except multiply and divide operations, while Pipe B executes ALU instructions and,
optionally, multiply and divide instructions. This approach allows a speedup of up to 30% (depending on the
characteristics of the application) just by recompiling the code. In critical functions that are hand-coded in
assembly language, The LX4280 can provide greater than 80% speedup over the single-issue LX4189
processor running at the same clock rate.
Features introduced in Lexra’s RISC product line support System-on-Chip (SoC) design, including customerdefined
Coprocessors and customer extensions to the MIPS ISA, are standard in the LX4280. Configuration
options include Extended-JTAG (EJTAG) support for debug and In-Circuit Emulation (ICE). Lexra’s
products include the same memory management stub (SMMU) as the LX4189.
Because the LX4280 executes the MIPS instruction set, a wide variety of third-party software tools are
available including compilers, operating systems, debuggers and in-circuit emulators. The assembler
extensions and a cycle accurate Instruction Set Simulator (ISS) are developed by Lexra. Programmers can
use “off-the-shelf” C Compilers for initial coding; then replace performance-critical loops with optimized
assembler code.

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