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The book is presented as follows:
Chapter 1 provides an introduction to the role of test within the
electronic/microelectronic engineering environment and highlights a number of
key trends. The trends in test are highlighted, along with an overview of key
actions.
Chapter 2 provides an overview of the key fabrication processes. Whilst not
aimed at being an exhaustive review of the field, it is aimed at identifying key
aspects relating to test program development, in particular those relating to process
induced circuit failure modes and test program development following a defect
oriented approach.
Chapter 3 overviews test program development for digital logic, both
combinational logic and sequential logic. The principles identified here are
relevant for later discussions into System on a Chip (SoC) test program
development.
Chapter 4 introduces semiconductor memory structures and test procedures.
Traditionally, memories have been discrete packaged devices which, when utilised
with a suitable processor, develop the basic operation of a computer system.
Increasingly, the move towards higher levels of integration is leading to memories
being provided as macro cells for placement alongside other circuitry on the same
silicon die, leading towards System on a Chip (SoC) and System in Package (SiP)
solutions that require extensive use of memory.
Chapter 5 introduces Analogue test. The key differences between digital and
analogue test are presented, along with the challenges that exist in the need to
develop suitable analogue circuit stimulus, to capture signals and to analyse results.
Chapter 6 provides a discussion into the combining of digital and analogue test
methods to provide the ability to test mixed-signal designs. In particular, data
converter test requirements and solutions are considered.
Chapter 7 discusses test procedures for digital and analogue Input/Output cells
which interface the core of the silicon die to the package. Such cells have particular
test requirements.
Chapter 8 further develops digital test concepts and introduces structured
approaches to test program development and linkages to design with the “Design
for Testability” (DFT) approach.
Chapter 9 discusses the problem with, and need for solutions to, the testing of
System on a Chip (SoC) devices. Essentially, the previous concepts are revisited,
limitations identified and the need to adopt structured DfT approaches in product
development identified.
Chapter 10 introduces test pattern generation and fault simulation techniques.
These activities are required as an input to the development of structural test
programs. Fault simulation provides an important input to the development of
structural test programs that aim to detect circuit faults rather than confirm the
circuit functionality. Digital fault simulation is well established for specific fault
models, whereas analogue and mixed-signal test still require more refinement.
Chapter 11 discusses the need for, and issues relating to, the use of Automatic
Test Equipment (ATE) for semiconductor devices. The need to understand the
structure of the ATE, along with the limitations, are key to the success of test
program application in a production environment, are identified.
Chapter 12 highlights the role of Test Economics as an aid to the development of
effective and cost efficient test programs. |
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发表于 2009-9-12 11:48:19
