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Sr. Analog SerDes IC Design Engineer
Responsibilities
- Sr. Analog SerDes IC Design Engineer responsible for design of analog and mixed-signal integrated circuits.
- Design of integrated circuits for SerDes transceiver with date rates greater than 5 Gbps, as well as PLL, DLL, CDR, (adaptive) equalizer, signal detect circuits, etc.
- Drive new products from individual block design to production release
- Interact with the layout team and guide the critical layout areas
- Work closely with test engineering to ensure testability during production
- Interact with chip architect and study industry standards to understand system requirements and perform feasibility study of new product proposals
- Provide silicon bench evaluation and troubleshooting
Requirements
- BSEE/MSEE/PhD and 7+ years experience in analog IC Design
- At least 3 years of prior experience designing SerDes related circuits
- Proven record of product release to production
- Understanding and previous experience with industry standards like PCI Express, XAUI, SATA, Fiber Channel, USB 3.0, etc. is a big plus
- Experience with analog and mixed signal simulation tools
- Fluent in English and Mandarin
Sr. Analog IC Design Engineer
Responsibilities
- Design of analog and mixed-signal integrated circuits
- Drive new products from individual block design to production release
- Interact with the layout team and guide the critical layout areas
- Work closely with test engineering to ensure testability during production
- Interact with chip architect and study industry standards to understand system requirements and perform feasibility study of new product proposals
- Provide silicon bench evaluation and troubleshooting
Requirements
- MSEE and 3+ years experience in analog IC Design
- At least 3 years of experience designing any of the following circuits: PLL, A/D, D/A, ADC, etc.
- Proven record of product release to production
- Understanding and previous experience with Test, Packaging, Reliability
- Experience with analog and mixed signal simulation tools
- Fluent in English and Mandarin
Sr. Digital IC design engineer
Responsibilities
- asic Design for digital processing
- Micro-architecture definition; working closely with system architects (Such as dsp)
- RTL design, verification/emulation, simulation, synthesis, timing, and silicon bring-up
Requirements
- At least five years working experience with logic design, simulation, synthesis and testing
- Proficiency in verilog and its simulation environment
- Proficiency in digital processing and electronic technologies is preferred
- Experience with low-power design
- Experience in RAM and MCU design is also preferred
- Self-motivated and good team player
Sr. Digital Design Engineer (PLC)
Responsibilities
- Take technical lead for digit ASIC design team;
- Work with analog/digital ASIC design team for new product development;
- Support test & product team with chip debugging, failure analysis, characterizations and product release efforts;
- Located in Shanghai , and report to Chief Engineer
Requirements
- Master degree or above in EE or related field;
- 5+ years of experience on IC design, PLC(Power Line communication) experience or in RAM and MCU design is preferred
- Good knowledge of hdl (Verilog ), DFT, test benches
- Experienced in VLSI project organization (version control, directory structure, project scripts, etc.)
- Basic knowledge of VLSI backend (layout, test engineering, product qualification)
- Able to define and document chip architecture.
- Experience with embedded processors and DSP is preferred
- Deep understanding of CAD tools and libraries; HDL simulator, synthesis and timing verification tools (NC verilog, primetime, synopsis, IO-standard cell libraries, memory compilers, etc. )
- Excellent understanding of written English and good spoken English
Digital Design Engineer (PLC)
Responsibilities
- Work with analog/digital ASIC design team for new product development;
- Support test & product team with chip debugging, failure analysis, characterizations and product release efforts
Requirements
- Master degree or above in EE or related field;
- 3+ years of experience on logic design, simulation, synthesis and testing;
- Basic knowledge of HDL ( Verilog ), DFT, Test benches.
- Able to define module architecture
- Familiar with HDL simulator, synthesis and timing verification tools ( NC verilog, primetime, synopsis )
- Experience in communication and electronic technologies is preferred
- Good understanding of written English and basic spoken English
Sr. Analog Design Engineer (PLC)
Responsibilities
- Take technical lead for the team working in the field of communication analog ASIC design;
- Work with digital design team and marketing team for new product development;
- Support test & product team with chip debugging, failure analysis, characterizations and product release efforts;
- Located in Shanghai
Requirements
- Master degree or above in EE or related field;
- 5+ years of experience on IC design; PLC(Power Line communication) experience preferred;
- Strong Experience in analog blocks design, such as ADC/DAC, voltage reference, Op-amp, and Linear filters, etc.
- Able to define and document analog module architecture and requirement.
- Good knowledge of layout, test engineering, lab test and product qualification
- Familiar with CAD tools, such as schematic capture, SPICE simulator (or equivalent transistor level circuit simulator), virtuoso and Matlab system building.
- Familiar with full flow of analog IC design, which is from spec building, architecture simulation, circuit schematic, spice simulation and back-simulation, layout, drc/lvs/lpe check and tape-out.
- Four design finalized in silicon preferred
- Excellent understanding of written English and good spoken English
Analog Power Mgmt IC Design Manager
- Analog Power Management IC Design Manager responsible for managing a group of analog designers as well as hands on design of analog and mixed-signal integrated circuits.
- Design of integrated circuits for non-isolated switching regulators using boost and buck topologies, charge pumps, battery chargers and linear regulators.
- Drive new products from individual block design to production release
- Supervising and coaching junior designers and interact with the layout team and guide the critical layout areas
- Work closely with test engineering to ensure testability during production
- Interact with chip architect to understand system requirements and perform feasibility study of new product proposals
- Provide guidance on silicon bench evaluation and troubleshooting
Requirements
- MSEE/PhD and 10+ years experience in analog IC Design
- At least 5 years of prior experience designing switching power controllers and/or regulators
- Proven record of product release to production
- Experience with analog and mixed signal simulation tools
- Willing to relocate to Shanghai , China
- Fluent in English and Mandarin
Senior Marketing/Systems Architect Manager
- Explore and develop new Market opportunities in any of the following areas:
•
Consumer Electronics •
Signal conditioning and measurement for Industrial applications and Automotive (e.g. metering, AMR-automatic Meter Reading with PLC-Power Line communication) - Research & analyze market evolution, technology trend, and competitor landscape;
- Identify new product opportunity and make new product proposal and differentiated product definition;
- Develop winning strategy for new product, marketing penetration and sustainable business growth
- Build strategic business relationships with technical and business decision makers at targeted customer accounts;
Requirements
- Master degree or above, in EE or related.
- 10+ years hands on experience in new product definition in one of the above field.
•
Ability to write product requirement spec •
Expertise and insight in system and application - Solid technical background and system design knowledge, deep understanding of customer requirements in their end products
- Well established customer relationship and network in related industry
- Excellent written and oral communication skills in both Chinese and English;
- Strong sense in deliver commitment and driver to win
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eetop公众号
创芯大讲堂
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发表于 2009-6-22 21:55:38
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