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发表于 2009-6-19 17:35:22
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I read the design report, but honestly, it is not that good.
First, parasitic resistance of inductor is not taken into account. That's the reason why the simulatied noise factor is only 0.12, which is not trustable for the real design.
Second, inductance value of L1 used as degeneration is too small, only 0.3 nH. It is easily overwhelmed by the bonding wire inductance.
Third, no design methodology for the sizing of transistor.
Fourth, velocity saturation is covered in the design, and the quation taking into mobility reduction is for linear region.
Fifth, output matching network should be calculated first, not resort to simulation directly.
Sixth, why the noise of cascode transistor could be neglected,actually, the gain of first stage is low. |
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发表于 2009-3-28 03:57:01
