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芯片精品文章合集(500篇!)    创芯人才网--重磅上线啦!
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有谁知道lx5280芯片(mips核)

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发表于 2009-2-15 21:38:56 | 显示全部楼层 |阅读模式

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有谁知道lx5280芯片(mips核)
发表于 2009-2-16 14:41:00 | 显示全部楼层
fffffffffff
发表于 2009-2-17 18:25:34 | 显示全部楼层
这个片子主频到多少?
头像被屏蔽
发表于 2009-2-20 22:37:52 | 显示全部楼层
提示: 作者被禁止或删除 内容自动屏蔽
发表于 2009-5-11 16:45:04 | 显示全部楼层
用的地方还挺多的,我用的是在rtl无线路由器芯片上的,特难调。
发表于 2009-6-22 23:57:36 | 显示全部楼层
LX5280 200 MHz push-button synthesis in .18um technology

[ 本帖最后由 hiwu.tw 于 2009-6-23 00:15 编辑 ]

LX5280PF.pdf

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Lx5280 32-bit RISC-DSP Core Product Features

发表于 2009-6-23 00:01:36 | 显示全部楼层
LX4180 155 MHz push-button synthesis in .25um technology
LX4189 266 MHz push-button synthesis in .18um technology
LX4280 200 MHz push-button synthesis in .18um technology

[ 本帖最后由 hiwu.tw 于 2009-6-23 00:14 编辑 ]

LX4180PF.pdf

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LX4189PF.pdf

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LX4280PF.pdf

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发表于 2009-6-23 00:19:45 | 显示全部楼层
LX4580         
fine-grained hardware multithreading (HMT)
400 MHz in .13um technology

The LX4580 fine-grained multithreaded processor was a cool internal processor         design that ran at 400 MHz with push-button synthesis in .13um technology

HMTWhitepaper016-JP.pdf

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发表于 2009-6-23 00:30:05 | 显示全部楼层
LX5280Features
  • High-performance 32-bit RISC-DSP core
  • Superscalar, dual-issue 32-bit embedded processor function, with dual Multiply Accumulate (MAC)
  • Operates at 200 MHz in a 0.18 um ASIC process and 33 MHz in a EP20K1000Eor larger device
  • Supports MIPSI instruction set architecture [size=-1](see note 1 below)
  • Supports MIPS16 code compression
  • Includes an optional dual-MAC engine
  • Includes optional EJTAG on-chip software debug functionality
  • Supported by industry standard development tools and real-time operatingsystems

General DescriptionThe LX5280 is a 32-bit reduced instruction set computer (RISC) digitalsignal processing (DSP) processorwhich executes the MIPS-I instruction set [size=-1](see note 1 below)with the RADIAXDSP extensions. It allowsdesigners to take advantage of a wide array of software developmenttoolsavailable from commercial suppliers to develop code for a high-speed,high-performance DSP function. Multiplication, division, and RADIAXoperations areperformed in hardware by a dual-MAC engine.
Like Lexra's other products, the LX5280 can be configured to execute MIPS16compressed code, and on-chip code debug can be performed on the LX5280 withthe configurable EJTAG block.
The combination of a 32-bit RISC and high-performance DSP architecture in asingle processor function eliminates the need for a separate DSP andmicrocontroller in many applications.  This architecture simplifies development andreduces system-on-chip size, cost, and power consumption.

Architecture Overview
The LX5280 megafunction is based on Lexra's high-performance LX-5280embedded processor architecture. The following are characteristics ofthe LX5280 CPU:
  • The LX5280 incorporates an eight-port     register file. Four 32-bit source operands can be supplied and four     destinations updated per cycle.
  • Instructions are executed by two parallel six-stage     pipelines. The pipelines are designed so that all internal     transactions and interfaces occur on the positive edge of the processor     clock. Two-phase clocks are not used.
  • The LX5280 extends the standard MIPS-I     exception handling model. There are eight additional hardware prioritized     interrupts, each with a dedicated interrupt vector. This improves real-time     interrupt response.
  • The LX5280 runs all code written for the Lexra LX4180, but up to 35% faster

The LX5280 can be configured with the following optional features:
  • The Lexra Bus Controller (LBC) connects     peripheral functions and secondary memories to the processor's own local     buses. It is a non-multiplexed, non-pipelined, and a non-parity-checked     bus that provides the easiest  protocol for design integration. On the processor     side, the easiest protocol provides a four word deep write buffer and control for byte     and half-word transfers. On the peripheral side, the LBC is designed to     interface easily with industry standard bus protocols, such as peripheral     component interconnect (PCI), universal serial bus (USB) and IEEE Std. 1394.
  • MIPS16 instruction compression reduces     program size by up to forty percent. On-chip programs require less memory,     resulting in cost saving for system-on-chip designs.
  • The LX5280 implements the industry standard     EJTAG 2.0.0 specification for full-speed debug with real-time instruction     trace.
  • The LX5280 is supported by development tools from Green Hills Software Inc., Wind River Systems, and Embedded Performance Inc.
发表于 2009-6-23 00:35:36 | 显示全部楼层
Lexra 5280 CPU core documentation

lx5280_1_9.pdf

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Lexra CPU core documentation

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