LOD effect for sub-micro design

littlej · 发表于 2008-12-13 21:24:25

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TSMC LOD introduction
1. What is LOD effect ?

LOD means “Length of OD region”. LOD effect shows

that devices with different LOD sizes will have different

electrical characteristics.

2. What is the impact of LOD effect on device performance ?
LOD effect is due to stress at STI edge. It mainly changes the mobility

of the devices. And sometimes it might also cause threshold voltage

shift in some special cases. Note that the influence of LOD on NMOS

and PMOS might be different.

3. What is the influence of LOD effect on circuit design ?

Designers might have to take LOD size into consideration in addition to

W and L. It is especially important for post-layout simulation. So far there

have been various simulators and layout extraction tools which could

facilitate the whole procedure.

[ 本帖最后由 littlej 于 2008-12-13 21:28 编辑 ]

amyqi · 发表于 2010-1-6 13:15:16

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mintonor · 发表于 2010-1-23 11:54:14

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com686 · 发表于 2010-4-9 14:32:45

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ytc999 · 发表于 2010-4-9 15:09:32

good ones

caunty · 发表于 2010-6-2 15:50:58

学习啦

chase_kinetic · 发表于 2010-6-2 23:02:52

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chase_kinetic · 发表于 2010-6-2 23:05:14

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sunnyliu2008 · 发表于 2010-6-8 17:11:40

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Jason_ke · 发表于 2010-6-22 16:01:59

找了许久了谢谢啦

LOD effect for sub-micro design

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