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ASYNCHRONOUS CIRCUIT DESIGN -- A CASE STUDY OF A FRAMEWORK CALLED ACK
by
Hans Jacobson
Abstract
As design systems have grown in complexity and clock speeds are constantly increasing, several
limitations to the conceptual framework of synchronous design have begun to be noticed.
Some notable problems due to higher performance demand are clock skew, power dissipation,
interfacing diculties and worst case performance. It is therefore not a surprise that the area
of asynchronous circuits and systems, which generally do not su er from these problems, is
experiencing a signi cant resurgence of interest and research activity. However, a number of
important problems have to be solved before asynchronous design methods can be successfully
transferred to the CAD industry. First, asynchronous circuit design should be based on
high level synthesis methods that are based on standard hdls, the same basis as used for
synchronous circuits. Second, tools to synthesize asynchronous circuits should be capable of
handling and generating ecient implementations for reasonably large designs, such as the ones
found in high-level synthesis benchmarks. This requires a method that o ers
exibility to use
di erent signaling protocols, to decompose large centralized controllers and to take advantage
of advances in standard logic synthesis. Third, where eciency is critical, it should be possible
to obtain customized complex-gate based circuits. Finally, in order to appeal to current VLSI
CAD tool users, asynchronous high level synthesis tools should be available as part of existing
CAD frameworks. In this thesis, a framework called ACK incorporating all these features is
presented. |
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发表于 2008-7-7 20:42:39
