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Icarus verilog is a Verilog simulation and synthesis tool. It operates as a compiler, compiling source code writen in Verilog (IEEE-1364) into some target format. For batch simulation, the compiler can generate an intermediate form called vvp assembly. This intermediate form is executed by the ``vvp'' command. For synthesis, the compiler generates netlists in the desired format.
具体介绍见：http://www.icarus.com/eda/verilog/ |
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创芯大讲堂
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发表于 2008-5-24 23:36:34
