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| Systemverilog for Verification, Second Edition
A Guide to Learning the Testbench Language Features
Spear, Chris
2nd ed., 2008, XXXVI, 436 p. 5 illus., Hardcover
ISBN: 978-0-387-76529-7
Not yet published. Available: May 2, 2008
| $129.00
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About this book
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Table of contents
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Sample pages
About this book
- Contains a new chapter on programs and interfaces
- Improves previous chapters with new sections on directed testbenches as well as OOP, layered, and random testbenches for an ATM switch
- Includes a new chapter on "Interfacing to C"
- Adds many new and improved examples and explanations to the previous edition
New! Expanded! Updated!
Based on the bestselling first edition this extensively revised second edition includes the relevant changes that apply to the 2008 version of the SystemVerilog Language Reference Manual (LRM). Significant changes include:
- The revision of nearly every explanation and code sample
- The inclusion of new chapters: "A Complete SystemVerilog Testbench" with a complete constrained random testbench for an ATM switch and "Interfacing with C" on the DPI (Directed Programming Interface)
- The addition of 70 new examples including larger ones such as a directed testbench at the end of chapter four
- An expanded index with 50% more entries and cross references
"As digital integrated circuits relentlessly march towards a billion transistors and beyond, Verilog testbenches are running out of steam. With logic verification taking more effort than design, moving to a higher level of abstraction is the only choice. SystemVerilog appears to be the winner in the high-level verification language market and "SystemVerilog for Verification" is the book that will take working professionals and students alike from basic Verilog to the sophisticated structures needed to verify large and complex designs."
Ronald W. Mehler, Professor of Electrical and Computer Engineering, California State University Northridge
"It can be difficult to improve upon a great book, but Chris has achieved that goal - the second edition of this book is even better than the first!
The explanations of abstract verification constructs are more detailed, and many more comprehensive examples make it easier to see how to apply SystemVerilog in object-oriented verification. The new chapter on the SystemVerilog Direct Programming Interface (DPI) is a very valuable addition. This second edition is a must-have book for every engineer involved in Verilog and SystemVerilog design and verification. The book serves well both as a general SystemVerilog reference and for learning object-oriented verification techniques. This book is such an invaluable reference, that my company includes a copy as part of the student training materials with every SystemVerilog verification course we teach!"
Stuart Sutherland, SystemVerilog Training Consultant, Sutherland hdl, Inc.
Chris Spear is a Verification Consultant for Synopsys, and has advised companies around the world on testbench methodology. He has trained hundreds of engineers on SystemVerilog’s verification constructs.
Testbenches are growing more complex. You need this book to keep up.
Includes nearly 500 code samples and 70 figures.
Written for:
Hardware and software engineers in electronic design
Keywords:
- Spear
- SystemVerilog
- methodology concepts
- testbenches
- verification
Summary: Excellent book except for ...
Rating: 4
a few non-compliant code examples that do not follow the IEEE LRM. With that said, overall the book contains a number of good examples and covers the SV language. It doesn't spend much time discussing methodology (which can be good or bad depending on what you're looking for).
In summary, decent reading and a good language reference. Definitely a lot better than the VMM book.
Summary: Good introduction -- 3 and half stars
Rating: 3
Book is a good introduction to system verilog for verification - though some typographical mistakes and some coding mistakes, make it bit flaky.
I would definately recommend this book - as it is the fastest way to get going around system verilog. One thing I like is that it is tied to any vendor specific methodology like RVM or AVM or VMM.
Summary: SystemVerilog
Rating: 4
Helpful for those migrating from verilog because
it compares the new concepts in relation to known concepts of verilog.
I liked the "bug" symbol that cautions against possible coding problems.
All systemverilog concepts are covered in the book with examples.
What is lacking is a practical usable example to build a complete simulation environment.
Summary: Add this to your HDL library!
Rating: 5
This book explains the basics of how to write advanced testbenches using SystemVerilog's Object Oriented programming capabilities. The book does a great job of helping to understand the basics of OO programming, and how OO can be applied to hardware verification. The book is full of tips on the right way to use SystemVerilog. This book should be required reading before picking up books on advanced verification methodologies, such as Janick Bergeron's book on SystemVerilog Verificaiton Methodology Manual.
I am the principle author of the companion to this book, "SystemVerilog for Design: A Guide to Using SystemVerilog for Hardware Design and Modeling", ISBN: 0387333991. My book covers the synthesis aspects of SystemVerilog, and Chris Spear's book covers the testbench side. Our two books are designed to go hand-in-hand. I strongly recommend Chris Spear's SystemVerilog for Verification book be added to your library! -- Stu Sutherland
Summary: Excellent Verification Book
Rating: 5
This book provides guidelines on how to use System Verilog verification features to create testbench through numerous examples in addition to very good explanation. This book is very easy to understand provided one has basic background.
The author indicates common mistakes by placing "bug" icon next to the topic, so that readers become aware of the pitfall right a way. I found it extremely useful.
This book helped me to write test bench using System Verilog in very short time. The author has met and exceeded the objective of the book.
I highly recommend this book for students/engineers who have basic knowledge in Verilog and want to achieve or enhance their skills on verification area.
I rate this book as 5 out of 5.
[ 本帖最后由 benemale 于 2008-4-24 19:04 编辑 ] |
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