发几个IEEE文章（都是最近的，关于锁相环/频率综合器/PLL)

ohyoung · 发表于 2008-4-15 14:45:29

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BIST for Measuring Clock Jitterof Charge-Pump Phase-Locked Loops

Abstract !a This paper presents a built-inself-test(BIST) circui that measures the clock jitter of the charge-pump phase-locked loops (PLLs).The jitter-measurement structureis based on a novel time-to-digital converter(TDC) which has a high resolution.A small area overhead is also achieved using the voltage-controlled oscillator and the loop filter of the PLL under test as parts of the TDC. The experiment result shows thatt here solutionis about 1ps and that the measurement error is smaller than 20%.

[ 本帖最后由 ohyoung 于 2008-4-19 14:05 编辑 ]

ohyoung · 发表于 2008-4-15 15:02:26

A Quantization Noise Pushing Technique for $DeltaSigma$ Fractional- $N$ Frequency Synthesizers
Yang, Y.-C. Lu, S.-S.
This paper appears in: Microwave Theory and Techniques, IEEE Transactions on
Publication Date: April 2008
Volume: 56 , Issue: 4
On page(s): 817 - 825
Number of Pages: 817 - 825
Location: Scottsdale, AZ, USA
ISSN: 0000-0000
Digital Object Identifier: 10.1109/TMTT.2008.918166
Posted online: 2008-04-04 11:46:48.0

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Abstract
This paper demonstrates our proposed quantization noise pushing technique, which moves the quantization noise to higher frequencies and utilizes the low-pass characteristic of the phased-lock loop (PLL) to further suppress the quantization noise. In addition, it can separate the operating frequency of the $DeltaSigma$ modulator and the comparison frequency of the phase/frequency detector (PFD) so as to reduce the loop gain of the PLL and lower the in-band phase noise. This synthesizer was fabricated using the UMC 0.18-$mu{hbox{m}}$ CMOS process. The chip area measures 0.85 ${hbox {mm}}^{2}$. The supply voltage is 2 V, corresponding to a total power consumption of 26.8 mW. The experimental results show that, with this technique, the in-band phase noise can be lowered by 12 dB, while the out-of-band phase noise can be reduced by more than 15 dB, compared to a synthesizer with the same PFD comparison frequency.

ohyoung · 发表于 2008-4-15 15:05:31

A Robust Single-Phase PLL System With Stable and Fast Tracking
Shinnaka, S.
This paper appears in: Industry Applications, IEEE Transactions on
Publication Date: March-april 2008
Volume: 44 , Issue: 2
On page(s): 624 - 633
Number of Pages: 624 - 633
ISSN: 0093-9994
Digital Object Identifier: 10.1109/TIA.2008.916750
Posted online: 2008-03-21 14:27:07.0

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Abstract
Phase, frequency, and amplitude of single-phase voltages are the most important and basic information required for single-phase grid-connected applications. This paper proposes a method for instantly and robustly estimating the phase, frequency, and amplitude of frequency-varying single-phase signals for such applications, which is a phase-locked loop (PLL) method based on a structure. The proposed method has the following attractive features: 1) the estimation system results in a nonlinear system, but it can be stabilized; 2) all subsystems constructing the system can be easily designed; 3) “two-phase signal generator” can autotune a single system parameter in response to varying frequency of the injected signal; 4) high-order “PLL-Controllers” allowing fast tracking can be stably used; and 5) even in hostile envelopments, favorable instant estimates can be obtained. This paper proposes the estimation method and verifies its usefulness by extensive numerical experiments.

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ohyoung · 发表于 2008-4-15 15:22:40

A Simplified Algorithm for Computing the Half-Plane Pull-In Range of a PLL
Stensby, John L.
Electrical and Computer Engineering Department, University of Alabama in Huntsville, Phone: 256 824 6258, e-mail: stensby@ece.uah.edu
This paper appears in: System Theory, 2008. SSST 2008. 40th Southeastern Symposium on
Publication Date: 16-18 March 2008
On page(s): 46 - 49
Number of Pages: 46 - 49
Location: New Orleans, LA, USA
ISSN: 0094-2898
ISBN: 978-1-4244-1807-7
Digital Object Identifier: 10.1109/SSST.2008.4480187
Posted online: 2008-04-04 11:46:04.0

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Abstract
For a second-order PLL with a lead-lag (ie., imperfect integrator) loop filter, the pull-in range ¿p and the half-plane pull-in range ¿2 are important parameters. Both parameters play key roles in determining if phase lock will (or can) occur once the loop is closed. For values of loop detuning ¿¿ that lie in the range 0 ¿ |¿¿| ≪ ¿p, the PLL will pull-in to phase lock from all values of initial phase error ¿(0) and frequency error ¿(0). That is, for 0 ¿ |¿¿| ≪ ¿p, pull-in will occur from all points on the (¿,¿) phase plane (hence the name pull-in range for ¿p). For values of loop detuning ¿¿ that lie in the range ¿p ≪ |¿¿| ≪ ¿2, the PLL will pull-in to phase lock from initial points that lie in a half-plane portion of the (¿,¿) phase plane (hence the name half-plane pull-in range for ¿2). In the literature, a numerical algorithm is described for computing ¿2. It involves a differential equation that becomes indeterminate at a saddle point from which a separatrix must be computed by using a complicated numerical procedure. In what follows, this algorithm is simplified by transforming the differential equation to remove the indeterminacy. The modified algorithm is applied, and numerical results are given for a practical and useful range of loop parameters.

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ohyoung · 发表于 2008-4-15 15:38:47

A Design Method and Developments of a Low-Power and High-Resolution Multiphase Generation System

Matsumoto, A. Sakiyama, S. Tokunaga, Y. Morie, T. Dosho, S.
This paper appears in: Solid-State Circuits, IEEE Journal of
Publication Date: April 2008
Volume: 43 , Issue: 4
On page(s): 831 - 843
Number of Pages: 831 - 843
Location: Lille, France
ISSN: 0018-9200
Digital Object Identifier: 10.1109/JSSC.2008.917567
Posted online: 2008-03-31 10:26:22.0

Abstract
A practical method for coupled oscillator design is elaborated. The topology analysis of a coupled oscillator, the ways of simulating its sensitivity, initializing its operation, and the oscillation frequency enhancement with nMOS phase couplers are presented. We have developed a write strategy system for DVD with a coupled oscillator using these techniques. In addition, we have also developed a low-power-oriented multiphase generator for mobile phones with our newly devised multiphase level shift system (M-LS). The M-LS has established superiority in its low power consumption because of no short current. Moreover, we have applied the method of output phase-accuracy improvement using a resistor ring to the M-LS. Two test chips are fabricated and the design method is validated. The first coupled oscillator has a resolution of 32 ps and a phase accuracy of $-$1.0 to 0.8 LSB at 490 MHz, corresponding to 16$times$ DVD write speed. The second one consumes 1 mA and has a high phase accuracy of 0.5 LSB at 123 MHz.

[ 本帖最后由 ohyoung 于 2008-4-15 16:51 编辑 ]