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[招聘] [AMD社招] Design Verification Engineer

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发表于 2018-4-16 16:18:04 | 显示全部楼层 |阅读模式

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Job Responsibilities:

AMDNBIO (North Bridge IO) team delivers industry leading high performanceinterconnects IP for all AMD products including dGPU, APU, Server and Gameconsoles. The candidate will be working with the global team on NBIO subsystemlevel verification

Responsibility:

*Subsystem level test plan development

*Work with architecture/IP designers to get a full deep insight on the designunder test

*Subsystem level test bench build, verification component build

*Verification leader of group

Education& Qualifications:


Candidate is preferred to be MSEE withminimum of 5 years, or BSEE with minimum of 8-year experience in digitalasic/SOC design verification.

  

Experience:

  

  

1.
Complex IP/ASIC/SOC Design Verification, direct  experience in IP/SOC or Processor (cpu or GPU) or Industry bus standard  (PCI-e, HT) is preferred.

  

2.
Good knowledge of UVM

  

3.
Good knowledge of verilog/C/C++/System  C/SystemVerilog.

  

4.
Verification insights into random techniques.

  

5.
Experience of verification lead is an asset.

  

6.
Experience of PCIe verification is an asset.

  

7.
Experience in power verification is an asset.

  

8.
Verification of Virtualization is an asset.

  

9.
Strong C and C++ software development and scripting  languages (Perl, C Shell, Makefile, …) experience.

  

10.
Solid background with hardware verification  methodologies such as coverage-based verification methodology with the use of  hardware assertions (PSL or SVA).

  

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