[AMD应届生] Design Verification Engineer

RecruiterAMD

AMD超威半导体招聘 Design Verification Engineer (应届生），请有意向者将简历发送到Cherry.Zhang@amd.comDesign Verification Engineer (Methodology)What you do at AMD changes everything At AMD, we push the boundaries of what is possible.  We believe in changing the world for the better by driving innovation in high-performance computing, graphics, and visualization technologies – building blocks for gaming, immersive platforms, and the data center. Developing great technology takes more than talent: it takes amazing people who understand collaboration, respect, and who will go the “extra mile” to achieve unthinkable results.  It takes people who have the passion and desire to disrupt the status quo, push boundaries, deliver innovation, and change the world.   If you have this type of passion, we invite you to take a look at the opportunities available to come join our team. RESPONSIBILITIES:•        Work with global Front-End design team and physical design team for large scale asic chip physical implementation.•        Focus on physical design of deep sub-micron GPU chips including block level (full chip) floor planning, timing closure, place&route, physical verification etc.•        Responsible for multiple aspects in PD areas and provide technically leadership to the engineering team.•        Aaccountable for project delivery.REQUIREMENTS:•        Familiar with Unix/Linux environment and good at scripts•        Understand the architecture of the chip and functional block being designed•        Build C/C++ model for simulation•        Build test bench and monitors for DUT•        Compose test plan and validation vectors to ensure functional completeness•        Debug function/performance bugs of graphics chips•        Preferred Experience:•        Familiar with Linux Environment (including shell scripting and linux gnu tools)•        Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)•        Should be versatile in any one of the high level verification flow such as SV,VMM,VERA,OVM etc as well as knowledge of industry standard tools for verification•        Should have excellent communication skills (both written and oral)•        Strong problem solving skillsEDUCATION:•        Major in EE, CS or related, Master Degree with 3+ years or Bachelor with 5+ years working experiences