|
|
马上注册，结交更多好友，享用更多功能，让你轻松玩转社区。
您需要 登录 才可以下载或查看，没有账号？注册
x
Report 在下面贴出来了，报的net错误在版图上都是一条线上的，麻烦大神帮着看一眼，谢啦~
LVS Netlist Compiler - Errors and Warnings for "/home/boshi51/digital_QRS/HCOMP/SAVE/all.cdl"
---------------------------------------------------------------------------------------------
Warning: Duplicate subckt definition "POST_DRIVER_16" at line 1296 in file "/home/boshi51/digital_QRS/HCOMP/SAVE/HDIOH2ING01V1.cdl"
##################################################
## ##
## C A L I B R E S Y S T E M ##
## ##
## L V S R E P O R T ##
## ##
##################################################
REPORT FILE NAME: HCOMP.lvs.report
layout NAME: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech/HCOMP.sp ('HCOMP')
SOURCE NAME: /home/boshi51/digital_QRS/HCOMP/SAVE/all.cdl ('HCOMP')
RULE FILE: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech/_be35_5.0v+40v_1p4m_calibre_lvs_v1.7_
CREATION TIME: Sat Jan 6 17:31:02 2018
CURRENT DIRECTORY: /home/boshi51/newpdk/HHGRACE_PDK_BCD350GE/tech
USER NAME: boshi51
CALIBRE VERSION: v2011.2_34.26 Wed Jul 6 05:20:56 PDT 2011
OVERALL COMPARISON RESULTS
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets.
Error: Connectivity errors.
Warning: Unbalanced smashed mosfets were matched.
**************************************************************************************************************
CELL SUMMARY
**************************************************************************************************************
Result Layout Source
----------- ----------- --------------
INCORRECT HCOMP HCOMP
**************************************************************************************************************
LVS PARAMETERS
**************************************************************************************************************
o LVS Setup:
// LVS COMPONENT TYPE PROPERTY
// LVS COMPONENT SUBTYPE PROPERTY
// LVS PIN NAME PROPERTY
LVS POWER NAME "VDD" "?VDD?" "VCC" "?VCC?"
LVS GROUND NAME "GND" "?GND?" "VSS" "?VSS?"
LVS CELL SUPPLY NO
LVS RECOGNIZE GATES ALL
LVS IGNORE PORTS NO
LVS CHECK PORT NAMES YES
LVS IGNORE TRIVIAL NAMED PORTS NO
LVS BUILTIN DEVICE PIN SWAP YES
LVS ALL CAPACITOR PINS SWAPPABLE NO
LVS DISCARD PINS BY DEVICE NO
LVS SOFT SUBSTRATE PINS NO
LVS INJECT LOGIC YES
LVS EXPAND UNBALANCED CELLS YES
LVS FLATTEN INSIDE CELL NO
LVS EXPAND SEED PROMOTIONS NO
LVS PRESERVE PARAMETERIZED CELLS NO
LVS GLOBALS ARE PORTS YES
LVS REVERSE WL NO
LVS SPICE PREFER PINS YES
LVS SPICE SLASH IS SPACE YES
LVS SPICE ALLOW FLOATING PINS YES
// LVS SPICE ALLOW INLINE PARAMETERS
LVS SPICE ALLOW UNQUOTED STRINGS NO
LVS SPICE CONDITIONAL LDD NO
LVS SPICE CULL PRIMITIVE SUBCIRCUITS NO
LVS SPICE IMPLIED MOS AREA NO
// LVS SPICE MULTIPLIER NAME
LVS SPICE OVERRIDE GLOBALS NO
LVS SPICE REDEFINE PARAM NO
LVS SPICE REPLICATE DEVICES NO
LVS SPICE SCALE X PARAMETERS NO
LVS SPICE STRICT WL NO
// LVS SPICE OPTION
LVS STRICT SUBTYPES NO
LVS EXACT SUBTYPES NO
LAYOUT CASE YES
SOURCE CASE YES
LVS COMPARE CASE NO
LVS DOWNCASE DEVICE NO
LVS REPORT MAXIMUM 50
LVS PROPERTY RESOLUTION MAXIMUM 32
// LVS SIGNATURE MAXIMUM
// LVS FILTER UNUSED OPTION
// LVS REPORT OPTION
LVS REPORT UNITS YES
// LVS NON USER NAME PORT
// LVS NON USER NAME NET
// LVS NON USER NAME INSTANCE
// Device Type Map
LVS DEVICE TYPE RESISTOR "RW" [ POS=POS NEG=NEG ] SOURCE LAYOUT
// Reduction
LVS REDUCE SERIES MOS YES
LVS REDUCE PARALLEL MOS YES
LVS REDUCE SEMI SERIES MOS NO
LVS REDUCE SPLIT GATES YES
LVS REDUCE PARALLEL BIPOLAR YES
LVS REDUCE SERIES CAPACITORS YES
LVS REDUCE PARALLEL CAPACITORS YES
LVS REDUCE SERIES RESISTORS YES
LVS REDUCE PARALLEL RESISTORS YES
LVS REDUCE PARALLEL DIODES YES
LVS REDUCE D(ZN) PARALLEL
LVS REDUCE PC PARALLEL
LVS REDUCE J(NJ) PARALLEL
LVS REDUCTION PRIORITY PARALLEL
LVS SHORT EQUIVALENT NODES NO
// Trace Property
TRACE PROPERTY q(4l) a a 1
TRACE PROPERTY q(pn) a a 1
TRACE PROPERTY q(vp) a a 1
TRACE PROPERTY q(4n) a a 1
TRACE PROPERTY q(4k) a a 1
TRACE PROPERTY q(p4) a a 1
TRACE PROPERTY m(sn) w w 10
TRACE PROPERTY m(sn) l l 10
TRACE PROPERTY m(sp) w w 10
TRACE PROPERTY m(sp) l l 10
TRACE PROPERTY m(mn) w w 10
TRACE PROPERTY m(mn) l l 10
TRACE PROPERTY md(de) w w 10
TRACE PROPERTY md(de) l l 10
TRACE PROPERTY m(snh) w w 10
TRACE PROPERTY m(snh) l l 10
TRACE PROPERTY m(sph) w w 10
TRACE PROPERTY m(sph) l l 10
TRACE PROPERTY m(mnh) w w 10
TRACE PROPERTY m(mnh) l l 10
TRACE PROPERTY md(deh) w w 10
TRACE PROPERTY md(deh) l l 10
TRACE PROPERTY m(2s) w w 10
TRACE PROPERTY m(2s) l l 10
TRACE PROPERTY m(4s) w w 10
TRACE PROPERTY m(4s) l l 10
TRACE PROPERTY m(h2) w w 10
TRACE PROPERTY m(h2) l l 10
TRACE PROPERTY m(so) w w 10
TRACE PROPERTY m(so) l l 10
TRACE PROPERTY ldd(i2) w w 10
TRACE PROPERTY ldd(i2) l l 10
TRACE PROPERTY ldd(i4) w w 10
TRACE PROPERTY ldd(i4) l l 10
TRACE PROPERTY lddd(dn4) w w 10
TRACE PROPERTY lddd(dn4) l l 10
TRACE PROPERTY ldd(xn) w w 10
TRACE PROPERTY ldd(xn) l l 10
TRACE PROPERTY ldd(x4) w w 10
TRACE PROPERTY ldd(x4) l l 10
TRACE PROPERTY ldd(ap) w w 10
TRACE PROPERTY ldd(ap) l l 10
TRACE PROPERTY ldd(4p) w w 10
TRACE PROPERTY ldd(4p) l l 10
TRACE PROPERTY ldd(ao) w w 10
TRACE PROPERTY ldd(ao) l l 10
TRACE PROPERTY ldd(4o) w w 10
TRACE PROPERTY ldd(4o) l l 10
TRACE PROPERTY ldd(sp24) w w 10
TRACE PROPERTY ldd(sp24) l l 10
TRACE PROPERTY ldd(sp30) w w 10
TRACE PROPERTY ldd(sp30) l l 10
TRACE PROPERTY ldd(sph30) w w 10
TRACE PROPERTY ldd(sph30) l l 10
TRACE PROPERTY ldd(sph40) w w 10
TRACE PROPERTY ldd(sph40) l l 10
TRACE PROPERTY ldd(snl24) w w 10
TRACE PROPERTY ldd(snl24) l l 10
TRACE PROPERTY ldd(snd12) w w 10
TRACE PROPERTY ldd(snd12) l l 10
TRACE PROPERTY ldd(snl30) w w 10
TRACE PROPERTY ldd(snl30) l l 10
TRACE PROPERTY ldd(snl40) w w 10
TRACE PROPERTY ldd(snl40) l l 10
TRACE PROPERTY ldd(snh30) w w 10
TRACE PROPERTY ldd(snh30) l l 10
TRACE PROPERTY ldd(snh40) w w 10
TRACE PROPERTY ldd(snh40) l l 10
TRACE PROPERTY mn(nn) w w 10
TRACE PROPERTY mn(nn) l l 10
TRACE PROPERTY mn(np) w w 10
TRACE PROPERTY mn(np) l l 10
TRACE PROPERTY mn(nm) w w 10
TRACE PROPERTY mn(nm) l l 10
TRACE PROPERTY mn(nd) w w 10
TRACE PROPERTY mn(nd) l l 10
TRACE PROPERTY m(op) w w 10
TRACE PROPERTY m(op) l l 10
TRACE PROPERTY m(s2) w w 10
TRACE PROPERTY m(s2) l l 10
TRACE PROPERTY m(s4) w w 10
TRACE PROPERTY m(s4) l l 10
TRACE PROPERTY m(vs) w w 10
TRACE PROPERTY m(vs) l l 10
TRACE PROPERTY ldde(e1) w w 10
TRACE PROPERTY ldde(e1) l l 10
TRACE PROPERTY ldde(e2) w w 10
TRACE PROPERTY ldde(e2) l l 10
TRACE PROPERTY ldde(e1n) w w 10
TRACE PROPERTY ldde(e1n) l l 10
TRACE PROPERTY ldde(e2n) w w 10
TRACE PROPERTY ldde(e2n) l l 10
TRACE PROPERTY ldde(ec) w w 10
TRACE PROPERTY ldde(ec) l l 10
TRACE PROPERTY ldde(ei) w w 10
TRACE PROPERTY ldde(ei) l l 10
TRACE PROPERTY ldde(ef) w w 10
TRACE PROPERTY ldde(ef) l l 10
TRACE PROPERTY ldde(eh) w w 10
TRACE PROPERTY ldde(eh) l l 10
TRACE PROPERTY j(nj) w jft_w 10
TRACE PROPERTY j(nj) l jft_l 10
TRACE PROPERTY d(d1) a a 1
TRACE PROPERTY d(d3) a a 1
TRACE PROPERTY d(d2) a a 1
TRACE PROPERTY d(zn) m m 0
TRACE PROPERTY c(c3) c c 1
TRACE PROPERTY c(c1) c c 1
TRACE PROPERTY c(c2) c c 1
TRACE PROPERTY pc c c 1
TRACE PROPERTY c(nc) c c 1
TRACE PROPERTY r(rh) r r 1
TRACE PROPERTY r(rm) r r 1
TRACE PROPERTY r(no) r r 1
TRACE PROPERTY r(po) r r 1
TRACE PROPERTY r(rn) r r 1
TRACE PROPERTY r(nr) r r 1
TRACE PROPERTY r(r1) r r 1
TRACE PROPERTY rw r r 1
TRACE PROPERTY r(fu) r r 1
TRACE PROPERTY r(r2) r r 1
TRACE PROPERTY r(r3) r r 1
TRACE PROPERTY r(r4) r r 1
CELL COMPARISON RESULTS ( TOP LEVEL )
# # #####################
# # # #
# # INCORRECT #
# # # #
# # #####################
Error: Different numbers of nets (see below).
Error: Connectivity errors.
Warning: Unbalanced smashed mosfets were matched.
LAYOUT CELL NAME: HCOMP
SOURCE CELL NAME: HCOMP
--------------------------------------------------------------------------------------------------------------
INITIAL NUMBERS OF OBJECTS
--------------------------
Layout Source Component Type
------ ------ --------------
Ports: 38 38
Nets: 32938 32945 *
Instances: 82515 83421 * M (4 pins)
------ ------
Total Inst: 82515 83421
NUMBERS OF OBJECTS AFTER TRANSFORMATION
---------------------------------------
Layout Source Component Type
------ ------ --------------
Ports: 38 38
Nets: 27402 27409 *
Instances: 68297 68297 M (4 pins)
4152 4152 SM2 (4 pins)
48 48 SM3 (5 pins)
6 6 SM4 (6 pins)
541 541 SPM_2_1 (5 pins)
17 17 SPM_2_1_1 (6 pins)
647 647 SPM_2_2 (6 pins)
8 8 SPM_2_2_1 (7 pins)
7 7 SPM_3_1 (6 pins)
10 10 SPM((2+1)*2) (7 pins)
------ ------
Total Inst: 73733 73733
* = Number of objects in layout different from number in source.
**************************************************************************************************************
INCORRECT OBJECTS
**************************************************************************************************************
LEGEND:
-------
ne = Naming Error (same layout name found in source
circuit, but object was matched otherwise).
**************************************************************************************************************
INCORRECT NETS
DISC# LAYOUT NAME SOURCE NAME
**************************************************************************************************************
1 Net 1265 intadd_17_A_14_
XU2904/o
--------------------------------------------------------------------------------------------------------------
2 Net 440 n2099
XU3520/o
--------------------------------------------------------------------------------------------------------------
3 Net 1249 intadd_17_A_17_
XU2897/o
--------------------------------------------------------------------------------------------------------------
4 Net 1266 intadd_17_A_15_
XU2902/o
--------------------------------------------------------------------------------------------------------------
5 Net X432/1269 n1437
XU2722/o
--------------------------------------------------------------------------------------------------------------
6 Net X432/901 n1985
XU3406/o
--------------------------------------------------------------------------------------------------------------
7 Net X433/810 intadd_17_A_16_
XU2899/o
**************************************************************************************************************
INFORMATION AND WARNINGS
**************************************************************************************************************
Matched Matched Unmatched Unmatched Component
Layout Source Layout Source Type
------- ------- --------- --------- ---------
Ports: 38 38 0 0
Nets: 27402 27409 0 0
Instances: 32799 32799 0 0 M(sn)
35498 35498 0 0 M(sp)
4152 4152 0 0 SM2
48 48 0 0 SM3
6 6 0 0 SM4
541 541 0 0 SPM_2_1
17 17 0 0 SPM_2_1_1
647 647 0 0 SPM_2_2
8 8 0 0 SPM_2_2_1
7 7 0 0 SPM_3_1
10 10 0 0 SPM((2+1)*2)
------- ------- --------- ---------
Total Inst: 73733 73733 0 0
o Statistics:
1743 layout mos transistors were reduced to 394. 5 connecting nets were deleted.
1339 mos transistors were deleted by parallel reduction.
10 mos transistors and 5 connecting nets were deleted by split-gate reduction.
3240 source mos transistors were reduced to 985. 5 connecting nets were deleted.
2245 mos transistors were deleted by parallel reduction.
10 mos transistors and 5 connecting nets were deleted by split-gate reduction.
o Initial Correspondence Points:
Ports: VCC VSS HCOMP_out[15] HCOMP_out[7] HCOMP_out[5] HCOMP_out[8] HCOMP_out[12]
HCOMP_out[2] HCOMP_out[10] HCOMP_out[6] HCOMP_out[4] HCOMP_out[13] HCOMP_out[3]
HCOMP_out[11] HCOMP_out[14] HCOMP_out[9] clk_div3 HCOMP_out[0] HCOMP_out[1]
HCOMP_in[15] HCOMP_in[14] HCOMP_in[13] HCOMP_in[7] HCOMP_in[8] HCOMP_in[9]
HCOMP_in[10] HCOMP_in[11] HCOMP_in[12] HCOMP_in[1] HCOMP_in[3] HCOMP_in[2]
HCOMP_in[4] reset HCOMP_in[5] HCOMP_in[6] HCOMP_in[0] clk_enable clk_div2
o Matched Mosfets Which Have Been Unequally Reduced:
X423/X1315/M3(311.270,1289.100) XFE_PHC131_n350/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC131_n350/MX1I6_M1I2
X423/X1314/M3(293.070,1243.980) XFE_PHC594_delay_pipeline_305_/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC594_delay_pipeline_305_/MX1I6_M1I2
X423/X1313/M3(285.270,1168.740) XFE_PHC658_delay_pipeline_277_/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC658_delay_pipeline_277_/MX1I6_M1I2
X423/X1312/M3(272.270,1168.740) XFE_PHC644_n309/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC644_n309/MX1I6_M1I2
X423/X1311/M3(247.570,1168.740) XFE_PHC615_n339/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC615_n339/MX1I6_M1I2
X423/X1310/M3(247.570,1163.700) XFE_PHC493_n325/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC493_n325/MX1I6_M1I2
X423/X1309/M3(247.570,1143.660) XFE_PHC477_n324/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC477_n324/MX1I6_M1I2
X423/X1308/M3(243.670,1269.060) XFE_PHC479_n352/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC479_n352/MX1I6_M1I2
X423/X1307/M3(235.870,1294.140) XFE_PHC593_n335/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC593_n335/MX1I6_M1I2
X423/X1306/M3(221.570,1168.740) XFE_PHC485_n322/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC485_n322/MX1I6_M1I2
X423/X1305/M3(215.070,1243.980) XFE_PHC272_delay_pipeline_306_/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC272_delay_pipeline_306_/MX1I6_M1I2
X423/X1304/M3(204.670,1238.940) XFE_PHC588_n338/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC588_n338/MX1I6_M1I2
X423/X1303/M3(191.670,1269.060) XFE_PHC596_n336/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC596_n336/MX1I6_M1I2
X423/X1302/M3(190.370,1264.020) XFE_PHC598_n337/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC598_n337/MX1I6_M1I2
X423/X1301/M3(190.370,1168.740) XFE_PHC433_n340/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC433_n340/MX1I6_M1I2
X423/X1300/M3(169.570,1168.740) XFE_PHC264_delay_pipeline_308_/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC264_delay_pipeline_308_/MX1I6_M1I2
X423/X1299/M3(168.270,1238.940) XFE_PHC599_delay_pipeline_307_/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC599_delay_pipeline_307_/MX1I6_M1I2
X423/X1298/M3(147.470,1213.860) XFE_PHC620_n354/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC620_n354/MX1I6_M1I2
X423/X1132/M3(1116.200,1163.700) XFE_PHC336_n460/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC336_n460/MX1I6_M1I2
X423/X1131/M3(1098.000,1168.740) XFE_PHC333_n444/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC333_n444/MX1I6_M1I2
X423/X1130/M3(1096.700,1238.940) XFE_PHC82_n445/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC82_n445/MX1I6_M1I2
X423/X1129/M3(1090.200,1193.820) XFE_PHC80_n237/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC80_n237/MX1I6_M1I2
X423/X1128/M3(1087.600,1213.860) XFE_PHC81_n461/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC81_n461/MX1I6_M1I2
X423/X1127/M3(1082.400,1269.060) XFE_PHC154_n253/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC154_n253/MX1I6_M1I2
X423/X1126/M3(938.100,1143.660) XFE_PHC700_n252/MX1I6_M1I2_0
** missing smashed mosfet ** XFE_PHC700_n252/MX1I6_M1I2
**************************************************************************************************************
SUMMARY
**************************************************************************************************************
Total cpu Time: 2 sec
Total Elapsed Time: 2 sec |
|
/3 
eetop公众号
创芯大讲堂
创芯人才网
发表于 2018-1-6 22:47:20
