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Job Tasks
Work with designer to get a full deep insight on the design and develop stressful test plan for SoC and IPs
Build test bench and create testcase to ensure maximum coverage
Run simulation in both RTL and netlist level, debug and fix issues, create test reports.
Develop verification IP which can be reused at different level verification
Co-work with FPGA engineer to prepare test vector, support test and debug
SoC system performance profiling, system stress test
Explore advanced verification methodology, optimize the verification process/environment to improve efficiency and quality
Support DV manager to do the verification quality control and sign-off the DV task
Qualifications
Must Have
MSEE/MSCS degree or equivalent
Minimum 8 years’ experience in design verification field
· Good knowledge in Systemverilog, C/C++ and UVM
· Good knowledge in the SoC architecture, AXI/AHB protocol. Experienced in full chip verification plan, execution and sign-off.
· Experienced in system performance test
· Strong communications skills and capability
Self-motivated and good team player
Nice to have
· Strong Programming in Perl, Python
· Good digital signal processing background and be familiar with video processing algorithm, be familiar with MATLAB
· Experienced in low power verification
· Be familiar with FPGA debug.
KT Human Resources Consulting Company (Shanghai) was established in 2001 in response to a need for a recruitment consultancy to be an active, contributing member of the semiconductor community, as opposed to simply a supplier to it.We provide professional search and talent acquisition in the Integrated Circuit、Electronic、Telecommunications industry of international corporations in Greater China. Our client list contains numerous international companies, many of them are long-term customers.
If you interested in the job, pls sent your cv to: hr@kthr.com, thanks!
“凯轶—KT咨询”微信也可查询职位啦!打开手机微信,搜号码“KTHR_COM”或查找微信公众帐号“凯轶—KT咨询”即可添加,欢迎大家关注!
或者直接扫我哦!
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