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Job Title: Manager, asic Digital Design (Timing, DFT Validation) Location: Wuhan Email: qyzhong@synopsys.com This position will be leading a global team to developtiming constrain validation and DFT validation platform for Synopsys leadingedge interface IP. PositionResponsibilities: ·
Drive andwork closely with RTL, implementation and methodology teams to establish a flowthat brings the RTL and STA constraints into the in-house infrastructure forSTA analysis ·
Use theregression infrastructure to provide feedback to the RTL team on thetiming-cleanliness of the design and the quality of the STA constraintsthemselves ·
Participatein the discussions/reviews of the regression results to improve the correct andefficiency of the flow ·
Beresponsible for ATPG pattern generation with good DFT fault coverage Requirements: Must have BSEE in EE with 7+years of relevant experience or MSEE with 5+ years of relevant experience inthe following areas: ·
Demonstratesgood communication skills in both Mandarin and English ·
Excellentskills in scripting and automation ·
Experienceswith timing/Synthesis constraints and floorplan-aware synthesis ·
Knowledgeof verilog and IC design development cycle ·
Demonstratesgood analysis and problem-solving skills ·
leadershipexperience, demonstrate strong desire to lead and drive for results ·
Experiencesand decent knowledge with DFT fault coverage analysis, tools and flow setup:Synopsys TetraMax, Z01X |