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Cadence 上海招聘若干资深/高级数字后端设计工程师
投递要求
简历命名:姓名 -学校- 学历 - 投递职位
发送简历至:job_china@cadence.com
资深/高级数字后端设计工程师
Position Description:
Perform physical design implementation, including floor planning, power grid design, place and route, clock tree synthesis, timing closure, power/signal integrity signoff, physical verification (DRC/LVS/Antenna), EM/IR signoff, DFM Closure.
The candidate will have the opportunity to work on many varieties of challenging designs, i.e. low power and high speed design. The responsibility includes participating in or leading next generation PHY IP physical design, methodology and flow development.
Position Requirements:
BS degree with 5~10+ years of applicable experience, MS degree with 4~8+ years of applicable experience in electrical engineering, microelectronics.
Experienced with asic design flow, hierarchical physical design strategies, and methodologies and understand deep sub-micron technology issues. Solid knowledge on LP Design, static timing analysis, EM/IR-Drop/crosstalk analysis, physical verification, DFM. Successful track records of taping out complex, 16nm/10nm/7nm chips.
Automation and programming-minded, solid coding experience in Makefile/Tcl/Tk/Perl.
Self-motivated, able to work independently or as a team player, excellent verbal and written communication skills in English.
公司介绍
Cadence Design Systems, Inc.(Nasdaq股票代码:CDNS)是全球领先的EDA 软件开发商以及半导体知识产权(IP)的领先供应商。全球知名半导体与电子系统公司均将Cadence软件作为其全球设计的标准。
Cadence公司总部位于美国加州圣荷塞市,在全球有近7000名员工,于1992年进入中国市场,建立了上海、北京、深圳分公司以及上海研发中心、北京研发中心。他们主要承担美国总部EDA软件研发任务,力争提供给用户更加完美的设计工具和全流程服务。
怀着青春梦想的你,准备好与芯片行业的最新技术亲密接触,并且成为最杰出团队的一员吗?那还等什么?快快加入Cadence大家庭!Cadence将为您提供最广阔的舞台! |
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