Cadence 上海招聘Lead/Principal Design Engineer-MMP/FPGA

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Cadence 上海招聘Lead/Principal Design Engineer-MMP/FPGA, 有意者请假简历发至541515639@qq.com, 邮件标题中请注明应聘职位，谢谢！

1.
Lead Design Engineer –Memory Modeling Portfolio(Req 13208, 13209)

  

Position Description:

1. Responsible for scheduling,designing, developing, and supporting IP models of system level memory such asSDRAM (LPDDR, HBM), NAND Flash (ONFI/QSPI/OSPI), eMMC, SD Card, DFI, and UFSmodels for use on hardware based verification products.

2. Also responsible forupdating, maintaining, documenting, and supporting existing system level memorymodel products.

3. Perform as individualcontributor for RTL design, verification, productizing, and documentation ofmemory IP.

4. Interface with internaland external customers to work on diverse problems and solutions related toemulation, simulation, or verification.

5. Perform as team membertoward cross verification of and cross training in memory IP as well as indeveloping and using lifecycle processes to ensure product quality.

  

Position Requirements:

Essential:

1. The position requiresBSEE, or equivalent, with a minimum of 4 yrs of industry experience indesigning hardware systems.

2. RTL design knowledge usingverilog/SystemVerilog is required along with experience using RTL verificationtools and flows.

3. Experience with team-widecollaboration tools and process. Drive and ability to schedule workload andplan own tasks effectively.

4. Must have excellentcommunication skills with both written and spoken English.

Strongly Recommended:

1. Verification experienceusing Cadence simulation and/or emulation products is highly desired. 2.Programming experience with scripting languages like Perl, TCL, C-shell isstrongly recommended. 3. Experience in memory sub-system design and operationis strongly recommended.

2.
Principal SolutionsEngineer- Protium (Req 13266)

  

Position Description:

The Protium PrincipalSolutions Engineer position is responsible for both creating and deployment newtechnology and solutions for Cadence Protium FPGA Prototyping Platform. The jobfunction involves the following:

1. Support customers andfield to map asic designs to Protium  FPGA prototyping platform

2. Create new solutions forProtium FPGA prototyping platform that involve creating RTL designs for FPGA,board designs for accessories or developing advanced prototyping flows andmethodologies

3. Working with R&D todefine and review future product capabilities

4. Manage beta programs andlaunch of new products

5. Prepare Cadence fieldresources for new deployments including AE training and collateral developmentlike application notes, reference designs, demos

6. Assist field and customerson root causing complex issues on Protium FPGA prototyping platform

Position Requirements:

1. The position requiresBSEE, or equivalent, with a minimum of 5 years of industry experience with FPGAbased hardware solutions. Must have excellent communication skills with bothwritten and spoken English.

2. Deep technical expertisein FPGA design for either Altera or Xilinx products is required. Expertknowledge in FPGA design methodologies including high speed design, serial protocolsand FPGA timing closure is also required.

3. Must have excellenthardware and system debug capabilities.

4. RTL design knowledge usingVerilog/SystemVerilog is required along with experience using RTL verificationtools and flows. Verification experience using Cadence simulation and/oremulation products is highly desired. Programming experience with scriptinglanguages like Perl, TCL, C-shell is strongly recommended.

3.
Principal DesignEngineer- FPGA Hardware (Req 13717)

  

Position Description:

This is a position in theVertical Solutions Engineering team (VSE) in the Hardware System Verificationbusiness unit. The VSE team develops FPGA based boards, known as SpeedBridgesthat connect the Palladium system to real world external systems. This positionis for a Principal Design Engineer with responsibilities related to developingFPGA based SpeedBridge boards. The role is based in Shanghai and will add toour expanding team of VSE engineers in our main R&D headquarters withinChina. The position is supported by local team managers and will work veryclosely with our product area team architects based in San Jose, California inthe USA.

Key responsibilities

1. To develop protocolexpertise and knowledge in a number of standard protocols such as USB, PCIe,Networking and MIPI.

2. To specialize in a few ofthese protocols to become an expert capable of designing complex FPGA basedsystems to connect our high-performance computing platform (Palladium) toexternal systems over the standard protocols being addressed.

3. Develop and leaddevelopment of entire FPGA designs and subsystems, from initial concept toproductization and customer deployment.

4. Developing techniques toconnect systems using protocol based methods to overcome speed differences inthe systems being connected

5. The ability to write clearconcise technical specifications in English for the FPGA system beingdeveloped. Ranging initially from smaller sub-systems to entire SpeedBridgedesigns

6.Be able to proposeinnovative solutions to system level issues relating to customer verificationof ASICs in complex system level hardware and software environments

7. The ability to communicateand work co-cooperatively with other leading experts in the local Shanghai teamand with globally remote managers and other team members in San Jose in the US

8. Possess excellent Verilogor System Verilog RTL design skills

9. Possess excellent FPGAdesign skills that include balancing performance, area, power, complexity andtiming in Xilinx and/or Altera FPGA's and their associated design tools

Position Requirements:

1. Bachelors inElectrical Engineering (or equivalent computer systems) + 10 years of relatedexperience; Masters + 7 years of related experience; PhD + 5 years of relatedexperience

2. Must have excellentEnglish communication skills, both written and verbal as reports andspecifications will be in English and there will be extensive internationalvideo conference collaboration with the US San Jose team

3. Technical expertise inFPGA design for either Altera or Xilinx products is required.

4. Experience in FPGA designmethodologies including high speed design, serial protocols and FPGA timingclosure is required.

5. Excellent RTL designknowledge using Verilog is required

6. Extensive experience inusing RTL simulation verification tools and flows is required

7. Knowledge of USB3.x and orUSB2.0 protocols and overall system level experience is desired.

8. Verification using Cadencesimulation products is desired.

9. Experience with scriptinglanguages like Python, Perl, TCL, Unix-shell is strongly recommended.

10. Experience with versioncontrol systems such as Subversion (SVN) is also desired.

11. Familiarity with PCBschematics and related board design would be useful but not required

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