1 Key Design-for-Test Flows and Methodologies
2 Running RTL Test Design Rule Checking
3 Running the Test DRC Debugger
4 Performing Scan Replacement
5 Pre-Scan Test Design Rule Checking
6 Architecting Your Test Design
7 Advanced DFT Architecture Methodologies
8 Wrapping Cores
9 On-Chip Clocking Support
10 Exporting Data to Other Tools
1 TetraMAX Overview
2 Running TetraMAX
3 Command Interface
4 ATPG Design Flow
5 Using Tcl With TetraMAX
6 On-Chip Clocking Support
7 Working With Design Netlists and Libraries
8 Using the Graphical Schematic Viewer
9 Using the Hierarchy Browser
10 Using the Simulation Waveform Viewer
11 STIL Procedure Files
12 Fault Lists and Faults
13 Fault Simulation
14 Test Pattern Data
15 Path Delay Fault and Hold-Time Testing
16 Quiescence Test Pattern Generation
17 Transition-Delay Fault ATPG
18 Running Distributed ATPG
19 Presistent Fault Model Support
20 Diagnosing Manufacturing Test Failures
21 Using Physical Data for Diagnostics
22 Using TetraMAX With the IC Compiler layout Viewer
23 Bridging Fault ATPG
24 Troubleshooting
25 Power-Aware ATPG
26 Using TetraMAX and DFTMAX Ultra Compression
A Test Concepts
B ATPG Design Guidelines
C Importing Designs From DFT Compiler
D Utilities
E STIL Language Support
F STIL99 Versus STIL
G Defective Chain Masking for DFTMAX
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发表于 2014-7-25 22:04:18
