PCIE核仿真，没有仿真结果

neufeifatonju · 发表于 2014-2-26 14:21:52

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在ISE14.4环境下，生成PCIE核，X8,2.5G。添加example_design，source，simulation。修改board_common.v，tests.v到其所在文件夹，如`include "E:/work/ISE/ISE14.4/PCIE_20140225/ipcore_dir/pcie/simulation/functional/board_common.v"；仿真，如图：
另，提示pci_exp_expect_tasks.v下：
initial
begin
  error_file_ptr = $fopen("error.dat");
  if (!error_file_ptr) begin
$write("ERROR: Could not open error.dat.\n");
$finish;
  end
end
和sample_tests1.v下：
else if(testname == "sample_smoke_test0")
begin

语法错误。
有做过的，还望详解一下，PCIE的仿真流程，参考文档和网上都没怎么讲这块，不胜感激！

neufeifatonju · 发表于 2014-2-26 14:23:25

电脑是32位，win7系统，4G内存，应该不是内存不够。

neufeifatonju · 发表于 2014-2-26 17:09:32

回复 3# 卖女孩的小火柴

没有波形啊，所以没法查，这是提示信息，望指教：
ISim P.49d (signature 0x8ef4fb42)
This is a Full version of ISim.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 353.  For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNTD is not equal to width 64 of actual signal trn_td.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 354.  For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNTREM is not equal to width 1 of actual signal trn_trem.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 549.  For instance pcie_7x_i/pcie_block_i/, width 128 of formal port TRNRD is not equal to width 64 of actual signal trn_rd.
WARNING: File "E:/work/ISE/ISE14.4/pcie_20140226/ipcore_dir/pcie/simulation/functional/pcie_pcie_7x.v" Line 550.  For instance pcie_7x_i/pcie_block_i/, width 2 of formal port TRNRREM is not equal to width 1 of actual signal trn_rrem.
ERROR

ortability:3 - This Xilinx application has run out of memory or has
encountered a memory conflict.  Current memory usage is 2093776 kb.  You can
try increasing your system's physical or virtual memory.  If you are using a
Win32 system, you can increase your application memory from 2GB to 3GB using
the /3G switch in your boot.ini file. For more information on this, please
refer to Xilinx Answer Record #14932. For technical support on this issue,
you can open a WebCase with this project attached at
http://www.xilinx.com/support.
ERROR: The simulation failed to launch for the following reason:
The Simulation shut down unexpectedly during initialization.  Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation.  If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.

The simulation has terminated.
ISim>

neufeifatonju · 发表于 2014-2-26 19:48:28

出来不了仿真波形，有人知道是怎么回事吗，ISE下面信息是：
Compiling module sys_clk_gen(halfcycle=5000)
Compiling module sys_clk_gen(offset=0,halfcycle=5...
Compiling module sys_clk_gen_ds(halfcycle=5000)
Compiling module board
Compiling module glbl
Time Resolution for simulation is 1ps.
Waiting for 1655 sub-compilation(s) to finish...
Compiled 2788 Verilog Units
Built simulation executable E:/ISE/kc705_pcie_20140226/board_isim_beh.exe
Fuse Memory Usage: 269756 KB
Fuse CPU Usage: 153234 ms
Launching ISim simulation engine GUI...
"E:/ISE/kc705_pcie_20140226/board_isim_beh.exe" -intstyle ise -gui -tclbatch isim.cmd -wdb "E:/ISE/kc705_pcie_20140226/board_isim_beh.wdb"
ISim simulation engine GUI launched successfully

Process "Simulate Behavioral Model" completed successfully

neufeifatonju · 发表于 2014-2-26 20:58:59

其他人仿真不会都用的是64位系统吧。
再有下面的错误什么意思，怎么处理，别的工程仿真正常，如GTX，MIG等。
错误如下：
ERROR: The simulation failed to launch for the following reason:
The Simulation shut down unexpectedly during initialization. Please review the ISim log (isim.log) for details.
Please shut down ISim and retry the simulation. If the problem persists, please contact Xilinx support.
Time resolution is 1 fs
No active Database
Unable to execute live simulation command.